Abstract: The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.

Abstract: The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.

Abstract: A method and a circuit layout on a substrate of a semiconductor wafer, suitable for reducing defects during a chemical mechanical polishing process. On the substrate, the circuit layout comprises a plurality of strips of first circuit structure and at least two strips of second circuit structure located on the substrate. Each of the strips of second circuit structure respectively links the front end and the rear end of the plurality of strips of the first circuit structure for the purpose of averaging polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during the chemical mechanical polishing process for reducing defects.