Abstract: An error correction circuit for detecting and correcting errors in a received BCH codeword comprises first and second syndrome generators for generating patterns of binary signals representative of first and second syndromes of the received BCH codeword. An error detector circuit utilizes the generated syndromes to determine whether the received codeword has no multi-bit errors. Single bit errors are corrected while multibit errors are only indicated. The single bit error is corrected by successively generating patterns of binary signals representative of the powers a.sup.k of a primitive number a where k=p-1, p-2, . . . 2, 1, 0 and where p is the number of bits in the received codeword. When the binary pattern representative of the first syndrome is identical to the binary pattern representative of a.sup.k for a particular value of k, the particular value k indicates the location of the single bit error in the received codeword.