Abstract: A CMP apparatus and process sequence. The CMP apparatus includes multiple polishing pads or belts and an in-line metrology tool which is interposed between adjacent polishing pads or belts in the apparatus. A material layer on each of multiple wafers is successively polished on the polishing pads or belts. The metrology tool is used to measure the thickness of a material layer being polished on each of successive wafers in a lot prior to the final polishing step, in order to precisely polish the layer to a desired target thickness at the final polishing step. This renders unnecessary an additional process cycle to polish the layer on each wafer to the desired target thickness. The metrology tool may be modularized as a unit with the polishing pads or belts.

Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Abstract: A CMP apparatus and process sequence. The CMP apparatus includes multiple polishing pads or belts and an in-line metrology tool which is interposed between adjacent polishing pads or belts in the apparatus. A material layer on each of multiple wafers is successively polished on the polishing pads or belts. The metrology tool is used to measure the thickness of a material layer being polished on each of successive wafers in a lot prior to the final polishing step, in order to precisely polish the layer to a desired target thickness at the final polishing step. This renders unnecessary an additional process cycle to polish the layer on each wafer to the desired target thickness. The metrology tool may be modularized as a unit with the polishing pads or belts.

Abstract: A CMP apparatus and process sequence. The CMP apparatus includes multiple polishing pads or belts and an in-line metrology tool which is interposed between adjacent polishing pads or belts in the apparatus. A material layer on each of multiple wafers is successively polished on the polishing pads or belts. The metrology tool is used to measure the thickness of a material layer being polished on each of successive wafers in a lot prior to the final polishing step, in order to precisely polish the layer to a desired target thickness at the final polishing step. This renders unnecessary an additional process cycle to polish the layer on each wafer to the desired target thickness. The metrology tool may be modularized as a unit with the polishing pads or belts.

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Abstract: A one-time feedback CMP process control method which contributes to uniformity in the quantity of material removed from wafers in a lot during semiconductor processing and is suitable for complex processes such as STI (shallow trench isolation) fabrication procedures, is disclosed. The method includes providing a plurality of wafers having a set of pilot wafers and a set of remaining wafers, polishing each of the pilot wafers according to an original process time, determining a compensation time for the pilot wafers, determining an update time by adding the compensation time to the original process time and polishing the set of remaining wafers according to the update time.

Abstract: A one-time feedback CMP process control method which contributes to uniformity in the quantity of material removed from wafers in a lot during semiconductor processing and is suitable for complex processes such as STI (shallow trench isolation) fabrication procedures, is disclosed. The method includes providing a plurality of wafers having a set of pilot wafers and a set of remaining wafers, polishing each of the pilot wafers according to an original process time, determining a compensation time for the pilot wafers, determining an update time by adding the compensation time to the original process time and polishing the set of remaining wafers according to the update time.

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract: A CMP apparatus and process sequence. The CMP apparatus includes multiple polishing pads or belts and an in-line metrology tool which is interposed between adjacent polishing pads or belts in the apparatus. A material layer on each of multiple wafers is successively polished on the polishing pads or belts. The metrology tool is used to measure the thickness of a material layer being polished on each of successive wafers in a lot prior to the final polishing step, in order to precisely polish the layer to a desired target thickness at the final polishing step. This renders unnecessary an additional process cycle to polish the layer on each wafer to the desired target thickness. The metrology tool may be modularized as a unit with the polishing pads or belts.

Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Abstract: In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.

Abstract: A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: A method for forming a barrier layer upon an electrode contact. There is first provided a silicon substrate layer having an electrode contact region formed within the silicon substrate layer. There is then formed over the silicon substrate layer a titanium layer, where the titanium layer contacts the electrode contact region of the silicon substrate layer. There is then processed thermally the titanium layer in a nitrogen containing atmosphere to form a titanium silicide layer in contact with the electrode contact region and a titanium nitride layer formed thereover, where the titanium layer is completely consumed in forming the titanium silicide layer and the titanium nitride layer. Finally, there is formed upon the titanium nitride layer a barrier layer.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.