Patents by Inventor Yih-Yuh (Kelvin) Doong

Yih-Yuh (Kelvin) Doong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10546792
    Abstract: Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the invention, an evaluation wafer is first manufactured by utilizing at least one non-product mask to process one or more layer(s) on the evaluation wafer, and subsequently utilizing at least one unaltered product mask to process an evaluation-region-of-interest on the evaluation wafer. The evaluation-region-of-interest is evaluated by measuring the state of one or more feature(s) in the evaluation-region-of-interest using voltage contrast inspection (VCi). The measurements are then used to identify failures in the evaluation-region-of-terest. In response to identifying a failure in the evaluation-region-of-interest, the manufacturing process is improved by modifying at least one parameter associated with at least one processing step and manufacturing product wafers utilizing the at least one processing step(s) with the at least one modified parameter(s).
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 28, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Yih-Yuh Kelvin Doong, Sheng-Che Lin
  • Publication number: 20180108580
    Abstract: Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the invention, an evaluation wafer is first manufactured by utilizing at least one non-product mask to process one or more layer(s) on the evaluation wafer, and subsequently utilizing at least one unaltered product mask to process an evaluation-region-of-interest on the evaluation wafer. The evaluation-region-of-interest is evaluated by measuring the state of one or more feature(s) in the evaluation-region-of-interest using voltage contrast inspection (VCi). The measurements are then used to identify failures in the evaluation-region-of-interest.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 19, 2018
    Inventors: Yih-Yuh Kelvin DOONG, Sheng-Che LIN
  • Patent number: 9847264
    Abstract: Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the invention, an evaluation wafer is first manufactured by utilizing at least one non-product mask to process one or more layer(s) on the evaluation wafer, and subsequently utilizing at least one unaltered product mask to process an evaluation-region-of-interest on the evaluation wafer. The evaluation-region-of-interest is evaluated by measuring the state of one or more feature(s) in the evaluation-region-of-interest using voltage contrast inspection (VCi). The measurements are then used to identify failures in the evaluation-region-of-interest.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 19, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Yih-Yuh (Kelvin) Doong, Sheng-Che Lin