Abstract: A video encoder with quality estimation is shown. The video encoder has a video compressor, a video reconstructor, a quality estimator, and an encoder top controller. The video compressor receives the source data of a video to generate compressed data. The video reconstructor is coupled to the video compressor for generation of playback-level data that is buffered for inter prediction by the video compressor, wherein the video reconstructor generates intermediate data and, based on the intermediate data, the video reconstructor generates playback-level data. The quality estimator is coupled to the video reconstructor to receive the intermediate data. Quality estimation is performed based on the intermediate data rather than the playback-level data. Based on the quality estimation result, the encoder top controller adjusts at least one video compression factor in real time.

Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.

Abstract: A display device includes a display panel. The display panel has a functional display area. The functional display area includes a plurality of display pixels and a plurality of light transmitting regions. The plurality of display pixels are around by the plurality of the light transmitting regions. A boundary between one of the plurality of display pixels and one of the plurality of light transmitting regions comprises an arc segment.

Abstract: A data processing apparatus includes a storage element and a clock controller. The storage element has storage partitions, including a first storage partition and a second storage partition. The clock controller controls clock driving of the first storage partition and the second storage partition. When a processing circuit is configured to operate in a first condition to process a first data sample with a first bit width, the clock controller enables clock driving of both of the first storage partition and the second storage partition. When the processing circuit is configured to operate in a second condition to process a second data sample with a second bit width, the clock controller enables clock driving of the first storage partition and disables clock driving of the second storage partition.

Abstract: A data processing apparatus includes a storage element and a clock controller. The storage element has storage partitions, including a first storage partition and a second storage partition. The clock controller controls clock driving of the first storage partition and the second storage partition. When a processing circuit is configured to operate in a first condition to process a first data sample with a first bit width, the clock controller enables clock driving of both of the first storage partition and the second storage partition. When the processing circuit is configured to operate in a second condition to process a second data sample with a second bit width, the clock controller enables clock driving of the first storage partition and disables clock driving of the second storage partition.