Abstract: A display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit of the at least one driving circuit provides a driving signal for a pixel circuit of the at least one pixel circuit. The driving circuit includes N-level shift registers cascaded with each other. N is greater than or equal to two. The pixel circuit provides a display signal for a display unit of the display panel. A shift register of the N-level shift registers includes at least one first transistor. The at least one first transistor includes at least one first active layer, and an active layer with a largest area among the at least one first active layer is a first preset active layer. The pixel circuit includes at least one second transistor. The at least one second transistor includes at least one second active layer.

Abstract: A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L6. A sixth area S6=L6×D6.

Abstract: A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.

Abstract: A display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. A length of a channel region of the second transistor is L2. Along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2.

Abstract: Provided are a display panel, a driving method thereof and a display device. The display panel includes: a pixel circuit and a light-emitting element, where the pixel circuit includes a light emitting control module, a drive module and a compensation module; the light emitting control module includes a first light emitting control module configured to selectively provide a first power supply signal for the drive module; the drive module is configured to provide a drive current for the light-emitting element and comprises a drive transistor; the compensation module is configured to compensate a threshold voltage of the drive transistor; and a working process of the pixel circuit includes a light emitting stage and a bias stage.

Abstract: A display panel and a display device are provided. The display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit provides a driving signal for a pixel circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes at least one first active layer, and an active layer with a largest area is a first preset active layer. The pixel circuit includes at least one second active layer, where an active layer with a largest area among active layers containing silicon is a second preset active layer, and an active layer with a largest area among active layers containing oxide semiconductor is a third preset active layer. The first preset active layer has an area greater than the second preset active layer and the third preset active layer.

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a base substrate, a first transistor, a second transistor, a pixel circuit, and a drive circuit. A first active layer of the first transistor includes silicon; and a second active layer of the second transistor includes an oxide semiconductor. A length of a channel region of the first transistor is LL a distance between a first gate electrode and the first active layer is D1, and a first area S1=L1×D1; and a length of a channel region of the second transistor is L2, a distance between a second gate electrode and the second active layer is D2, and a second area S2=L2×D2, where S1<S2. The second transistor is included in the drive circuit, and the first transistor is included in one of the pixel circuit and the drive circuit.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. A shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit comprises a first gating unit. One terminal of the first gating unit is connected to a preset node, another terminal of the first gating unit is connected to a fourth node, and a control terminal of the first gating unit is configured to receive a fifth voltage signal. The second control unit is configured to receive at least a third voltage signal and a signal of the fourth node or receive at least a fourth voltage signal and a signal of a fifth node and generate an output signal.

Abstract: A display panel includes a driving circuit including N stages of cascaded shift registers, and each shift register includes: a first control part and a second control part; the second control part is configured to at least receive the signal of the second node, the signal of the third node, and a frequency control signal to generate an output signal; one shift register of the cascaded shift registers connected to a display unit in the first region is configured to receive the first frequency control signal, and one shift register of the cascaded shift registers connected to a display unit in the second region is configured to receive the second frequency control signal; a data refresh frequency of the display unit in the first region is F1, and a data refresh frequency in the second region is F2, F1<F2.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. A shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit is configured to receive at least a signal of a preset node and a first output control signal and control a signal of a fourth node. During at least part of a time period during which the signal of the fourth node is a low level signal, each of a signal of the preset node and the first output control signal is a low level signal.

Abstract: A display panel includes a driving circuit including N stages of cascaded shift registers, and each shift register includes: a first control part and a second control part; the second control part is configured to at least receive the signal of the second node, the signal of the third node, and a frequency control signal to generate an output signal; one shift register of the cascaded shift registers connected to a display unit in the first region is configured to receive the first frequency control signal, and one shift register of the cascaded shift registers connected to a display unit in the second region is configured to receive the second frequency control signal; a data refresh frequency of the display unit in the first region is F1, and a data refresh frequency in the second region is F2, F1<F2.

Abstract: A display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, N?2. A shift register of the N levels of the shift registers includes a third control unit and a fourth control unit. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node. The first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The fourth control unit is configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node and includes a first transistor and a second transistor.

Abstract: A display panel includes a shift register, a pixel circuit, and a driving circuit. The shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node.

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. the display panel further includes a first voltage signal line, providing a first voltage signal for the driving circuit; a second voltage signal line, providing a second voltage signal for the driving circuit; a third voltage signal line, providing a third voltage signal for the driving circuit; and a fourth voltage signal line, providing a fourth voltage signal for the driving circuit. At least one of the third voltage signal line and the fourth voltage signal line is disposed on a side of at least one of the first voltage signal line and the second voltage signal line facing toward a display region of the display panel.

Abstract: A display panel includes a pixel circuit and a driving circuit. The pixel circuit includes a driving transistor. The driving circuit is configured to provide a signal for the pixel circuit, receive a third voltage signal and a fourth voltage signal, and generate an output signal. The third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal. A working process of the pixel circuit includes a reset phase and a bias phase. The output signal of the driving circuit is a reset signal in the reset phase. The output signal of the driving circuit is a bias signal in the bias phase. In response to the driving transistor being a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. Each shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit is configured to receive a signal of a preset node and a first output control signal and control a signal of a fourth node, where the preset node is one of a second node or a third node. A first output control signal received by a shift register at an M1-th stage is a signal of the preset node of a shift register at an M2-th stage, where 1?M1?N, 1?M2?N, 1?|M1?M2|?i, and 2?i?N?1.

Abstract: In the pixel circuit, first terminal of drive module configured to receive signal output by first power supply, first light emission control module connected between second terminal of drive module and first terminal of light emitting module, and second terminal of light emitting module connected to second power supply; first terminal of first storage module connected to control terminal of drive module, second terminal of first storage module connected to first terminal of second storage module, and second terminal of second storage module connected to first terminal of light emitting module; threshold detection module connected between second terminal of first storage module and second terminal of drive module, and configured to control first storage module to store threshold voltage of drive module; data writing module connected to second terminal of drive module; an initialization module connected to control terminal of drive module and first terminal of light emitting module.

Abstract: Provided are a display panel and a display device. The display panel includes a driving circuit. The driving circuit includes N stages of cascaded shift registers. Each shift register includes a first control unit, a second control unit, and a third control unit. The first control unit is configured to receive a third voltage signal and control a signal of a fourth node in response to a frequency control signal. The second control unit is configured to receive a fourth voltage signal and control a signal of a fifth node in response to the frequency control signal. The third control unit is configured to receive a fifth voltage signal and generate an output signal in response to a signal of the fourth node; or the third control unit is configured to receive a sixth voltage signal and generate an output signal in response to a signal of the fifth node.

Abstract: Disclosed are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element, in the pixel circuit, the drive device includes a drive transistor; the reset device includes a first double-gate transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node. The pixel circuit is connected to a first power supply voltage signal terminal, and is configured to receive a first power supply voltage signal, and the first power supply voltage signal is a constant high level signal; and the pixel circuit includes a first capacitor, a first pole plate of the first capacitor is connected to the first power supply voltage signal terminal, and a second pole plate of the first capacitor is connected to the second node.

Abstract: Disclosed are a display panel and a display device. The display panel includes a pixel circuit. In the pixel circuit, a reset device includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node; a compensation device includes a third sub-transistor and a fourth sub-transistor, a connection node between the third sub-transistor and the fourth sub-transistor is a third node; the pixel circuit includes a second capacitor and a third capacitor; two pole plates of the second capacitor are respectively connected to a line of first scan signal and the second node; two pole plates of the third capacitor are respectively connected to a line of second scan signal and the third node; and the second capacitor (C2) and the third capacitor (C3) satisfy: C2?C3.