Patents by Inventor Yi-Hui Lin

Yi-Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210485
    Abstract: A communication device includes a plurality of dies, a composite substrate and at least one antenna. The composite substrate includes a PCB, a redistribution layer and a connecting layer. The connecting layer is configured to electrically connect the redistribution layer and the PCB. Each die is electrically connected to the redistribution layer. The distribution layer corresponding to each die is formed integrally. The PCB is disposed between the antenna and the redistribution layer. The antenna is electrically connected to the dies through the composite substrate. A manufacturing method of the composite substrate is also provided.
    Type: Application
    Filed: December 29, 2023
    Publication date: June 26, 2025
    Applicant: AUO Corporation
    Inventors: Shih-Hsien Yang, Yi-Cheng Lai, Chung-Hung Chen, Yu-Chih Wang, Yi-Hui Lin, Shuo-Yang Sun, Zong-Long Jhang
  • Publication number: 20250192434
    Abstract: An antenna device includes a transparent substrate and a plurality of antenna units disposed on the transparent substrate. The transparent substrate has a first surface and a second surface opposite to the first surface. A light-transmitting area is provided between adjacent antenna units. Each antenna unit includes an antenna electrode, a ground electrode, a redistribution structure, and a chip. The antenna electrode is disposed on the first surface of the transparent substrate. The ground electrode is disposed on the second surface of the transparent substrate. A width of the ground electrode in a first direction is greater than a width of the antenna electrode in a first direction. The redistribution structure is coupled to the antenna electrode. The ground electrode is located between the redistribution structure and the transparent substrate. The chip is bonded to the redistribution structure.
    Type: Application
    Filed: October 13, 2024
    Publication date: June 12, 2025
    Applicant: AUO Corporation
    Inventors: Shih-Hsien Yang, Chung-Hung Chen, Yi-Cheng Lai, Yu-Chih Wang, Yi-Hui Lin, Shuo-Yang Sun, Zong-Long Jhang
  • Publication number: 20250192435
    Abstract: A transparent antenna device includes a transparent substrate, an antenna electrode layer, an active device layer, a redistribution structure and a chip. The antenna electrode layer is located on the first surface of the transparent substrate and includes an antenna electrode located in a circuit layout region of the transparent antenna device. The active device layer is located above the second surface of the transparent substrate and includes an active device located in the circuit layout region. The redistribution structure is located on the active device layer and includes a signal line and a pad located in the circuit layout region. The chip is bonded to the pad of the redistribution structure and is located in the circuit layout region. The transparent antenna device has a light transmitting region located next to the circuit layout region.
    Type: Application
    Filed: October 29, 2024
    Publication date: June 12, 2025
    Applicant: AUO Corporation
    Inventors: Zong-Long Jhang, Hsiu-Yin Cheng, Yi-Hui Lin
  • Publication number: 20240411858
    Abstract: A whitelisting method for blocking script-based malware includes steps of: checking a command line of a process to confirm the process to launch a first interception point of a startup script file; checking whether the startup script file in a whitelist at the first interception point; determining that a test is passed when the startup script file exists in the whitelist, and launching the startup script file, wherein the startup script file at least includes a module script file; confirming the process to invoke a module loader to import and launch a second interception point of the module script file; checking whether the module loader is allowed to import the module script file, or is allowed to launch the module script file that has been imported by using the whitelist at the second interception point.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 12, 2024
    Inventors: Yi-Hui LIN, Kun-Ying LIN, Chia-Lin LIANG, Lap-Chung LAM, Tzi-Cker CHIUEH
  • Patent number: 11069660
    Abstract: A display device includes a first substrate, a first active element layer, first to third light-emitting elements, a first pixel defining layer, and fourth to sixth light-emitting elements. The first active element layer is disposed on the first substrate. The first, second and third light-emitting elements are electrically connected with the first active element layer. The first, second and third light-emitting elements have first, second and third light-emitting layers respectively. The first pixel defining layer is disposed on the first active element layer and has first, second and third openings. The first, second and third light-emitting layers are disposed in the first, second and third openings respectively. The fourth, fifth and sixth light-emitting elements are disposed on the first pixel defining layer. A vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Au Optronics Corporation
    Inventors: Yu-Ching Wang, Yi-Hui Lin
  • Patent number: 10862064
    Abstract: An organic light emitting diode (OLED) display panel includes a substrate, a reflective electrode disposed on the substrate, and a pixel define layer (PDL) formed on the substrate and the reflective electrode layer. The reflective electrode layer has multiple reflective structures, and each reflective structure has a first region and a second region. The PDL is provided with multiple openings corresponding to the reflective structures, such that the first region and the second region of each of the reflective structures are exposed in a corresponding one of the openings. Multiple organic emissive structures are correspondingly formed in the openings and covering the reflective structures, forming a plurality of pixels. For each respective pixel of the pixels, a first reflective ratio of the respective pixel corresponding to the first region is greater than a second reflective ratio of the respective pixel corresponding to the second region.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 8, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yung-Sheng Ting, Yu-Ching Wang, Yi-Hui Lin
  • Publication number: 20200258864
    Abstract: A display device includes a first substrate, a first active element layer, first to third light-emitting elements, a first pixel defining layer, and fourth to sixth light-emitting elements. The first active element layer is disposed on the first substrate. The first, second and third light-emitting elements are electrically connected with the first active element layer. The first, second and third light-emitting elements have first, second and third light-emitting layers respectively. The first pixel defining layer is disposed on the first active element layer and has first, second and third openings. The first, second and third light-emitting layers are disposed in the first, second and third openings respectively. The fourth, fifth and sixth light-emitting elements are disposed on the first pixel defining layer. A vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers.
    Type: Application
    Filed: July 26, 2019
    Publication date: August 13, 2020
    Applicant: Au Optronics Corporation
    Inventors: Yu-Ching Wang, Yi-Hui Lin
  • Patent number: 10043888
    Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Hui Lin, Keng-Jen Lin, Yu-Ren Wang
  • Publication number: 20180182862
    Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 28, 2018
    Inventors: Yi-Hui Lin, Keng-Jen Lin, Yu-Ren Wang
  • Patent number: 9847247
    Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 19, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
  • Publication number: 20170243780
    Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.
    Type: Application
    Filed: May 9, 2017
    Publication date: August 24, 2017
    Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
  • Patent number: 9685319
    Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
  • Patent number: 9543408
    Abstract: A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Hui Lin, Keng-Jen Lin, Chun-Yao Yang, Yu-Ren Wang
  • Publication number: 20160365245
    Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.
    Type: Application
    Filed: July 22, 2015
    Publication date: December 15, 2016
    Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
  • Patent number: 9349599
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160133474
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 12, 2016
    Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 8972734
    Abstract: A symmetric dynamic authentication and key exchange system and a method thereof are provided. A client and a server obtain initial authentication information at the same time, the client generates first one-time temporary authentication information, a conference key and a standby identity identifier according to the initial authentication information, and transmits them to the server, and the server performs a dynamic authentication program.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 3, 2015
    Assignee: National Sun Yat-Sen University
    Inventors: Chun-I Fan, Ruei-Hau Hsu, Yi-Hui Lin
  • Publication number: 20140115337
    Abstract: A symmetric dynamic authentication and key exchange system and a method thereof are provided. A client and a server obtain initial authentication information at the same time, the client generates first one-time temporary authentication information, a conference key and a standby identity identifier according to the initial authentication information, and transmits them to the server, and the server performs a dynamic authentication program.
    Type: Application
    Filed: June 25, 2013
    Publication date: April 24, 2014
    Inventors: Chun-I Fan, RUEI-HAU HSU, YI-HUI LIN
  • Publication number: 20030050875
    Abstract: The present invention is a method of sales deposit management. It is applied in a computer system and comprises the following steps. First, the data of the client's order is input to the computer system first. Then a new sales order record comprising a sales deposit record is produced based on the order information from the client. And a new sales deposit collection record is produced based on the sales deposit record and the details of client's deposit payment. Next a new record of sales deposit collection voucher and a new record of sales deposit invoice are produced based on the sales deposit collection record. A new delivery record as the reference for product delivery is produced based on the sales order record subsequently. And based on the delivery record and the sales deposit invoice record, a sales invoice record for the client is produced to complete the invoice-issuing process.
    Type: Application
    Filed: March 20, 2002
    Publication date: March 13, 2003
    Applicant: Via Technologies, Inc.
    Inventors: Yeun-Jonq Lee, Yueh-Wen Chen, Yi-Hui Lin
  • Publication number: 20020183892
    Abstract: A method for booking stocks by using a stock operation system in a computer comprises the steps of: a stock query information is firstly keyed into the stock operating system, wherein the stock query information includes the number or name of an item/product. Then, the stock operating system calculates statistically a offers and needs information of the item/product and shows the offers and needs information of the item/product on a monitor, where the offers and needs information of the item/product includes the information of the required quantity, booked quantity and lacked quantity of this item/product, etc. Subsequently, a stock adjustment information is keyed into the stock operating system, wherein the stock adjustment information includes the information for increase and reduction of the booked quantity of the item/product.
    Type: Application
    Filed: December 12, 2001
    Publication date: December 5, 2002
    Applicant: Via Technologies, Inc.
    Inventors: Yeun-Jonq Lee, Yueh-Wen Chen, Yi-Hui Lin