Patents by Inventor Yi-Hui Lin
Yi-Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140782Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: PO CHEN YEH, YI-HSIEN CHANG, FU-CHUN HUANG, CHING-HUI LIN, CHIAHUNG LIU, SHIH-FEN HUANG, CHUN-REN CHENG
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Patent number: 11955401Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.Type: GrantFiled: March 13, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
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Patent number: 11942375Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.Type: GrantFiled: August 17, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie, Chih-Yung Lin
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Patent number: 11069660Abstract: A display device includes a first substrate, a first active element layer, first to third light-emitting elements, a first pixel defining layer, and fourth to sixth light-emitting elements. The first active element layer is disposed on the first substrate. The first, second and third light-emitting elements are electrically connected with the first active element layer. The first, second and third light-emitting elements have first, second and third light-emitting layers respectively. The first pixel defining layer is disposed on the first active element layer and has first, second and third openings. The first, second and third light-emitting layers are disposed in the first, second and third openings respectively. The fourth, fifth and sixth light-emitting elements are disposed on the first pixel defining layer. A vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers.Type: GrantFiled: July 26, 2019Date of Patent: July 20, 2021Assignee: Au Optronics CorporationInventors: Yu-Ching Wang, Yi-Hui Lin
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Patent number: 10862064Abstract: An organic light emitting diode (OLED) display panel includes a substrate, a reflective electrode disposed on the substrate, and a pixel define layer (PDL) formed on the substrate and the reflective electrode layer. The reflective electrode layer has multiple reflective structures, and each reflective structure has a first region and a second region. The PDL is provided with multiple openings corresponding to the reflective structures, such that the first region and the second region of each of the reflective structures are exposed in a corresponding one of the openings. Multiple organic emissive structures are correspondingly formed in the openings and covering the reflective structures, forming a plurality of pixels. For each respective pixel of the pixels, a first reflective ratio of the respective pixel corresponding to the first region is greater than a second reflective ratio of the respective pixel corresponding to the second region.Type: GrantFiled: April 30, 2020Date of Patent: December 8, 2020Assignee: AU OPTRONICS CORPORATIONInventors: Yung-Sheng Ting, Yu-Ching Wang, Yi-Hui Lin
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Publication number: 20200258864Abstract: A display device includes a first substrate, a first active element layer, first to third light-emitting elements, a first pixel defining layer, and fourth to sixth light-emitting elements. The first active element layer is disposed on the first substrate. The first, second and third light-emitting elements are electrically connected with the first active element layer. The first, second and third light-emitting elements have first, second and third light-emitting layers respectively. The first pixel defining layer is disposed on the first active element layer and has first, second and third openings. The first, second and third light-emitting layers are disposed in the first, second and third openings respectively. The fourth, fifth and sixth light-emitting elements are disposed on the first pixel defining layer. A vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers.Type: ApplicationFiled: July 26, 2019Publication date: August 13, 2020Applicant: Au Optronics CorporationInventors: Yu-Ching Wang, Yi-Hui Lin
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Patent number: 10043888Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.Type: GrantFiled: December 27, 2016Date of Patent: August 7, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Hui Lin, Keng-Jen Lin, Yu-Ren Wang
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Publication number: 20180182862Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.Type: ApplicationFiled: December 27, 2016Publication date: June 28, 2018Inventors: Yi-Hui Lin, Keng-Jen Lin, Yu-Ren Wang
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Patent number: 9847247Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: GrantFiled: May 9, 2017Date of Patent: December 19, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Publication number: 20170243780Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: ApplicationFiled: May 9, 2017Publication date: August 24, 2017Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Patent number: 9685319Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: GrantFiled: July 22, 2015Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Patent number: 9543408Abstract: A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.Type: GrantFiled: August 26, 2015Date of Patent: January 10, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Hui Lin, Keng-Jen Lin, Chun-Yao Yang, Yu-Ren Wang
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Publication number: 20160365245Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: ApplicationFiled: July 22, 2015Publication date: December 15, 2016Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Patent number: 9349599Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.Type: GrantFiled: November 10, 2014Date of Patent: May 24, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
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Publication number: 20160133474Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.Type: ApplicationFiled: November 10, 2014Publication date: May 12, 2016Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
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Patent number: 8972734Abstract: A symmetric dynamic authentication and key exchange system and a method thereof are provided. A client and a server obtain initial authentication information at the same time, the client generates first one-time temporary authentication information, a conference key and a standby identity identifier according to the initial authentication information, and transmits them to the server, and the server performs a dynamic authentication program.Type: GrantFiled: June 25, 2013Date of Patent: March 3, 2015Assignee: National Sun Yat-Sen UniversityInventors: Chun-I Fan, Ruei-Hau Hsu, Yi-Hui Lin
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Publication number: 20140115337Abstract: A symmetric dynamic authentication and key exchange system and a method thereof are provided. A client and a server obtain initial authentication information at the same time, the client generates first one-time temporary authentication information, a conference key and a standby identity identifier according to the initial authentication information, and transmits them to the server, and the server performs a dynamic authentication program.Type: ApplicationFiled: June 25, 2013Publication date: April 24, 2014Inventors: Chun-I Fan, RUEI-HAU HSU, YI-HUI LIN
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Publication number: 20030050875Abstract: The present invention is a method of sales deposit management. It is applied in a computer system and comprises the following steps. First, the data of the client's order is input to the computer system first. Then a new sales order record comprising a sales deposit record is produced based on the order information from the client. And a new sales deposit collection record is produced based on the sales deposit record and the details of client's deposit payment. Next a new record of sales deposit collection voucher and a new record of sales deposit invoice are produced based on the sales deposit collection record. A new delivery record as the reference for product delivery is produced based on the sales order record subsequently. And based on the delivery record and the sales deposit invoice record, a sales invoice record for the client is produced to complete the invoice-issuing process.Type: ApplicationFiled: March 20, 2002Publication date: March 13, 2003Applicant: Via Technologies, Inc.Inventors: Yeun-Jonq Lee, Yueh-Wen Chen, Yi-Hui Lin
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Publication number: 20020183892Abstract: A method for booking stocks by using a stock operation system in a computer comprises the steps of: a stock query information is firstly keyed into the stock operating system, wherein the stock query information includes the number or name of an item/product. Then, the stock operating system calculates statistically a offers and needs information of the item/product and shows the offers and needs information of the item/product on a monitor, where the offers and needs information of the item/product includes the information of the required quantity, booked quantity and lacked quantity of this item/product, etc. Subsequently, a stock adjustment information is keyed into the stock operating system, wherein the stock adjustment information includes the information for increase and reduction of the booked quantity of the item/product.Type: ApplicationFiled: December 12, 2001Publication date: December 5, 2002Applicant: Via Technologies, Inc.Inventors: Yeun-Jonq Lee, Yueh-Wen Chen, Yi-Hui Lin