Patents by Inventor Yij Chieh Chu

Yij Chieh Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8756028
    Abstract: A fault detection method of semiconductor manufacturing processes is disclosed. The method includes the steps of providing a storage device, collecting a fault detection and classification(FDC) parameter by the storage device, setting up a measurement site for measuring an online measurement parameter, collecting a wafer acceptance test(WAT) in correspondence to the FDC parameter, establishing a first relationship equation between the FDC parameter and the online measurement parameter, establishing a second relationship equation of the online measurement parameter and the WAT by using the first relationship equation, establishing a third relationship equation between the FDC parameter and the WAT, establishing a waning region of the manufacturing processes by using the first, second, and third relationship equations, and determining the situation of generating wafer defects according to the warning region. The present invention discloses a system architecture for the method.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: June 17, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Yij Chieh Chu, Yun-Zong Tian
  • Patent number: 8649990
    Abstract: A method of detecting variance by regression model has the following steps. Step 1 is preparing the FDC data and WAT data for analysis. Step 2 is figuring out what latent variable effect of WAT data by Factor Analysis Step 3 is utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components. Step 4 is demonstrating how the tools and FDC data affect WAT data by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 11, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Yij Chieh Chu, Chun Chi Chen, Yun-Zong Tian
  • Patent number: 8510610
    Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: August 13, 2013
    Assignee: Inotera Memories, Inc.
    Inventors: Yij Chieh Chu, Yun-Zong Tian
  • Publication number: 20120331357
    Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.
    Type: Application
    Filed: September 22, 2011
    Publication date: December 27, 2012
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, YUN-ZONG TIAN
  • Publication number: 20120330591
    Abstract: A fault detection method of semiconductor manufacturing processes is disclosed. The method includes the steps of providing a storage device, collecting a fault detection and classification(FDC) parameter by the storage device, setting up a measurement site for measuring an online measurement parameter, collecting a wafer acceptance test(WAT) in correspondence to the FDC parameter, establishing a first relationship equation between the FDC parameter and the online measurement parameter, establishing a second relationship equation of the online measurement parameter and the WAT by using the first relationship equation, establishing a third relationship equation between the FDC parameter and the WAT, establishing a waning region of the manufacturing processes by using the first, second, and third relationship equations, and determining the situation of generating wafer defects according to the warning region. The present invention discloses a system architecture for the method.
    Type: Application
    Filed: September 22, 2011
    Publication date: December 27, 2012
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, YUN-ZONG TIAN
  • Patent number: 8332416
    Abstract: A specification establishing method for controlling semiconductor process, the steps includes: sampling a plurality of sample groups from a population, each sample group being a non-normal distribution; filtering the sample groups; summarizing the filtered sample groups to form a non-normal distribution diagram; getting a value-at-risk and a median by calculating from the non-normal distribution diagram; getting a critical value by calculating the value-at-risk and the median with a critical formula; getting a plurality of state values by calculating the filtered sample groups with a proportion formula; and getting an index value by calculating the non-normal distribution diagram with the proportion formula. Thus, the state values indicate the states of the sample groups are abnormal or not by comparing the state values to the index value.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 11, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Cheng-Hao Chen, Yun-Zong Tian, Shih-Chang Kao, Yij Chieh Chu, Wei Jun Chen
  • Patent number: 8265903
    Abstract: A method for assessing data worth for analyzing yield rate includes: getting measured data with data points that corresponds to control variables of semiconductor manufacturing; transforming the data points into a distance matrix with matrix distances corresponding to differences of the data points under the control variables; expressing sample differences recorded in the distance matrix by two-dimension vectors and calculating similarity degrees of the two-dimension vectors and the distance matrix so as to take loss information as a conversion error value; calculating discriminant ability of the transformed two-dimension data and expressing the discriminant ability by an error rate of discriminant; and taking the conversion error value and the error rate of discriminant as penalty terms and calculating a quality score corresponding to the measured data.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: September 11, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Yij Chieh Chu, Chun Chi Chen, Yun-Zong Tian, Shih Chang Kao, Cheng-Hao Chen
  • Patent number: 8244500
    Abstract: A method of adjusting wafer process sequence includes steps of collecting production parameters for a plurality of lots; selecting a plurality of key parameters from the production parameters, wherein the key parameters at least includes a processing sequence; defining a formula to obtain an epsilon value; categorizing the lots into groups according to the epsilon value and the minimum point number by using density-based spatial clustering of application with noise (DBSCAN); and adjusting the processing sequences of the lots in the groups. Thereby, the lots with the same process recipe can be continuously or simultaneously sent into a machine, thereby reducing replacement of process recipes or shortening machine idle time.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: August 14, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Yun-Zong Tian, Chun Chi Chen, Yi Feng Lee, Wei Jun Chen, Shih Chang Kao, Yij Chieh Chu, Cheng-Hao Chen
  • Publication number: 20120102052
    Abstract: A specification establishing method for controlling semiconductor process, the steps includes: providing a database and choosing a population from the database; sampling a plurality of sample groups from the population, each sample group being a non-normal distribution and having a plurality of samples; filtering the sample groups; summarizing the filtered sample groups to form a non-normal distribution diagram; getting a value-at-risk and a median by calculating from the non-normal distribution diagram; getting a critical value by calculating the value-at-risk and the median with a critical formula; getting a plurality of state values by calculating the filtered sample groups with a proportion formula; and getting an index value by calculating the non-normal distribution diagram with the proportion formula. Thus, the state values indicate the states of the sample groups are abnormal or not by comparing the state values to the index value.
    Type: Application
    Filed: January 11, 2011
    Publication date: April 26, 2012
    Applicant: INOTERA MEMORIES, INC.
    Inventors: CHENG-HAO CHEN, YUN-ZONG TIAN, SHIH-CHANG KAO, YIJ CHIEH CHU, WEI JUN CHEN
  • Publication number: 20110257932
    Abstract: A method of detecting variance by regression model has the following steps. Step 1 is preparing the FDC data and WAT data for analysis. Step 2 is figuring out what latent variable effect of WAT data by Factor Analysis Step 3 is utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components. Step 4 is demonstrating how the tools and FDC data affect WAT data by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN
  • Publication number: 20110251708
    Abstract: A method for planning a production schedule of equipment includes: receiving information about a material replacement of the equipment; and determining a target production schedule of the equipment according to the information about the material replacement of the equipment, wherein the target production schedule includes an idle period, and during the idle period, the equipment stops manufacturing under a normal state.
    Type: Application
    Filed: May 19, 2010
    Publication date: October 13, 2011
    Inventors: Wei-Jun Chen, Yun-Zong Tian, Yij-Chieh Chu, Yi-Feng Lee
  • Publication number: 20110153660
    Abstract: A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor pro
    Type: Application
    Filed: March 4, 2011
    Publication date: June 23, 2011
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN, CHENG-HAO CHEN
  • Publication number: 20110137595
    Abstract: A yield loss prediction method includes: performing a plurality of types of defect inspections upon a plurality of batches of wafers which begin to be processed during different periods to generate defect inspection data, respectively; for a specific batch of wafers different from the plurality of batches of wafers, calculating defect prediction data of at least one type of defect inspection according to the defect inspection data of at least the type of defect inspections; and predicting a yield loss of the specific batch of wafers according to at least the defect prediction data.
    Type: Application
    Filed: March 16, 2010
    Publication date: June 9, 2011
    Inventors: Yij-Chieh Chu, Yun-Zong Tian, Shih-Chang Kao, Wei-Jun Chen, Cheng-Hao Chen
  • Publication number: 20110093226
    Abstract: A fault detection and classification (FDC) method for wafer acceptance test (WAT) parameters includes the following steps. A plurality of fault detection and classification parameters is collected. A plurality of wafer acceptance test parameters that are corresponded by the fault detection and classification parameters is collected. The fault detection and classification parameters are grouped. A contingency table of the wafer acceptance test parameters corresponding to the fault detection and classification parameters is built. A probability model of the contingency table is built. Finally, a safety range of the probability model is determined.
    Type: Application
    Filed: December 27, 2010
    Publication date: April 21, 2011
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH-CHU, CHUN CHI CHEN, YUN-ZONG TIAN, CHENG-HAO CHEN
  • Publication number: 20100268501
    Abstract: A method for assessing data worth for analyzing yield rate includes: getting measured data with data points that corresponds to control variables of semiconductor manufacturing; transforming the data points into a distance matrix with matrix distances corresponding to differences of the data points under the control variables; expressing sample differences recorded in the distance matrix by two-dimension vectors and calculating similarity degrees of the two-dimension vectors and the distance matrix so as to take loss information as a conversion error value; calculating discriminant ability of the transformed two-dimension data and expressing the discriminant ability by an error rate of discriminant; and taking the conversion error value and the error rate of discriminant as penalty terms and calculating a quality score corresponding to the measured data.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 21, 2010
    Inventors: Yij Chieh Chu, Chun Chi Chen, Yun-Zong Tian, Shih Chang Kao, Cheng-Hao Chen
  • Publication number: 20100256792
    Abstract: A method of adjusting wafer process sequence includes steps of collecting production parameters for a plurality of lots; selecting a plurality of key parameters from the production parameters, wherein the key parameters at least includes a processing sequence; defining a formula to obtain an epsilon value; categorizing the lots into groups according to the epsilon value and the minimum point number by using density-based spatial clustering of application with noise (DBSCAN); and adjusting the processing sequences of the lots in the groups. Thereby, the lots with the same process recipe can be continuously or simultaneously sent into a machine, thereby reducing replacement of process recipes or shortening machine idle time.
    Type: Application
    Filed: June 2, 2009
    Publication date: October 7, 2010
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YUN-ZONG TIAN, CHUN CHI CHEN, YI FENG LEE, WEI JUN CHEN, SHIH CHANG KAO, YIJ CHIEH CHU, CHENG-HAO CHEN
  • Publication number: 20100223027
    Abstract: A monitoring method for multi tools is disclosed. The method includes the steps of providing a plurality of measurement tools for measuring the testing points of standard wafers, calculating a vector for representing a measurement tool, calculating the angle between every two of the vectors and determining the measurement tools having the same performance or not. Thereby, the measurement tools can be efficiently grouped and the measuring stability of the measurement tool is analyzed.
    Type: Application
    Filed: May 26, 2009
    Publication date: September 2, 2010
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN, SHIH CHANG KAO, CHENG-HAO CHEN
  • Publication number: 20100093114
    Abstract: A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor pro
    Type: Application
    Filed: December 9, 2008
    Publication date: April 15, 2010
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN, CHENG-HAO CHEN
  • Publication number: 20100049355
    Abstract: A method for determining manufacturing tool production quality includes providing a table with manufacturing process data. The table is analyzed and a contingency table is established. The contingency table comprises several manufacturing tools, manufacturing processes, and the number of occurrences of bad lots. Split the contingency table up into a plurality of sub-tables. Use Cochran-Mantel-Haenszel test for determining the number of bad lots produced by the manufacturing tools and getting a plurality of statistics. Translate the statistics into a plurality of P-values. Sort the P-values for examining data automatically. Draw a line chart for detecting substandard manufacturing tools. As a result, users can diagnose the quality of the manufacturing tools.
    Type: Application
    Filed: November 24, 2008
    Publication date: February 25, 2010
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN, CHENG-HAO CHEN
  • Publication number: 20100010763
    Abstract: A method of detecting variance by regression model is disclosed. Said method comprising: preparing the FDC and WAT data for analysis, figuring out what latent variable effect WAT by Factor Analysis, utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components, demonstrating how the tool and FDC affect WAT by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.
    Type: Application
    Filed: September 2, 2008
    Publication date: January 14, 2010
    Applicant: INOTERA MEMORIES INC.
    Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN, YI FENG LEE