Patents by Inventor Yikai Liang
Yikai Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11835595Abstract: A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.Type: GrantFiled: August 11, 2022Date of Patent: December 5, 2023Assignee: Shanghai Biren Technology Co., LtdInventors: Kai Lei, Yikai Liang, Yudan Deng, Linglan Zhang, Jinfu Ye, Huan Liu
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Publication number: 20230176118Abstract: A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.Type: ApplicationFiled: August 16, 2022Publication date: June 8, 2023Applicant: Shanghai Biren Technology Co.,LtdInventors: Kai LEI, Yikai LIANG, Yudan DENG, Linglan ZHANG, Jinfu YE, Huan LIU
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Publication number: 20230176141Abstract: A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.Type: ApplicationFiled: August 11, 2022Publication date: June 8, 2023Applicant: Shanghai Biren Technology Co.,LtdInventors: Kai LEI, Yikai LIANG, Yudan DENG, Linglan ZHANG, Jinfu YE, Huan LIU
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Publication number: 20220404857Abstract: A semiconductor die is provided. The semiconductor die includes a D2D transceiver composed of a single die or dual dies. The D2D transceiver includes a first D2D transmitter and a first D2D receiver. The D2D transmitter is configured to send data to a second D2D receiver in a second D2D transceiver of another semiconductor die using a first reference clock signal. The D2D receiver is configured to receive data from a second D2D transmitter in the second D2D transceiver using a second reference clock signal. Through using the embodiments of the disclosure, a transmission solution may be flexibly configured for a multi-application scenario including D2D.Type: ApplicationFiled: June 13, 2022Publication date: December 22, 2022Applicant: Shanghai Biren Technology Co.,LtdInventors: Yikai Liang, Junhai Liu, Wenqi Li, Linglan Zhang, Dongcai Li, Zheng Tian
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Patent number: 11381245Abstract: The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.Type: GrantFiled: September 8, 2021Date of Patent: July 5, 2022Assignee: Shanghai Biren Technology Co., LtdInventors: Zheng Tian, YiKai Liang, Linglan Zhang, WenQi Li, DongCai Li, TingTing Yu
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Patent number: 8829941Abstract: A method is provided for receiving a differential signal pair input at a first circuit stage and converting the differential signal pair input to a single-ended signal at a second circuit stage. The method also provides for receiving an output of the first circuit stage and an output of the second stage at a third circuit stage and transmitting an amplified signal output from the third circuit stage. The method allows for a 60 dB signal gain or more. A circuit is also provided that includes multiple circuit stages that can provide signal gain to an input differential signal pair. The circuit converts the differential pair into a single-ended signal and transmits the amplified signal as an output. The circuit provides the signal gain without using a current mirror. A computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus is also provided.Type: GrantFiled: December 10, 2011Date of Patent: September 9, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Xin Liu, Arvind Bomdica, Yikai Liang
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Patent number: 8570067Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.Type: GrantFiled: May 15, 2007Date of Patent: October 29, 2013Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Oleg Drapkin, Grigori Temkine, Marcus Ng, Kevin Yikai Liang, Arvind Bomdica, Siji Menokki Kandiyil, Ming So, Samu Suryanarayana
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Patent number: 8564583Abstract: A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.Type: GrantFiled: December 17, 2009Date of Patent: October 22, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Kevin Yikai Liang, Xin Liu, Arvind Bomdica, Ming-Ju Edward Lee
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Publication number: 20130147554Abstract: A method is provided for receiving a differential signal pair input at a first circuit stage and converting the differential signal pair input to a single-ended signal at a second circuit stage. The method also provides for receiving an output of the first circuit stage and an output of the second stage at a third circuit stage and transmitting an amplified signal output from the third circuit stage. The method allows for a 60 dB signal gain or more. A circuit is also provided that includes multiple circuit stages that can provide signal gain to an input differential signal pair. The circuit converts the differential pair into a single-ended signal and transmits the amplified signal as an output. The circuit provides the signal gain without using a current mirror. A computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus is also provided.Type: ApplicationFiled: December 10, 2011Publication date: June 13, 2013Inventors: Xin Liu, Arvind Bomdica, Yikai Liang
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Patent number: 8432207Abstract: Methods and apparatuses are provided for duty cycle correction of high-speed clock circuits. The apparatus includes a duty cycle interpolator receiving a clock source for providing a duty cycle corrected clock signal. The duty cycle corrected clock signal is filtered and compared to a reference signal, the result of which is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to the duty cycle interpolator for adjusting the duty cycle of the clock signal to provide the duty cycle corrected clock signal. The method includes filtering a duty cycle corrected clock signal to provide a filtered signal and comparing the filtered signal to a reference signal, the result of is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to a duty cycle interpolator for adjusting the duty cycle of a clock signal.Type: GrantFiled: December 30, 2011Date of Patent: April 30, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Jackie Chu, Yikai Liang
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Patent number: 8149024Abstract: A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.Type: GrantFiled: December 8, 2009Date of Patent: April 3, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Xin Liu, Arvind Bomdica, Yikai Liang, Ming-Ju Edward Lee, Rohit Rathi, Jinyung Namkoong
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Patent number: 8102633Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.Type: GrantFiled: March 18, 2009Date of Patent: January 24, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
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Patent number: 8102632Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices.Type: GrantFiled: March 18, 2009Date of Patent: January 24, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
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Publication number: 20110148838Abstract: A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Kevin Yikai Liang, Xin Liu, Arvind Bomdica, Ming-Ju Edward Lee
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Publication number: 20110133788Abstract: A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.Type: ApplicationFiled: December 8, 2009Publication date: June 9, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Xin Liu, Arvind Bomdica, Yikai Liang, Ming-Ju Edward Lee, Rohit Rathi, Jinyung Namkoong
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Publication number: 20100238599Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.Type: ApplicationFiled: March 18, 2009Publication date: September 23, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
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Publication number: 20100238598Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices.Type: ApplicationFiled: March 18, 2009Publication date: September 23, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
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Patent number: 7714615Abstract: A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.Type: GrantFiled: February 18, 2008Date of Patent: May 11, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Yikai Liang, Arvind Bomdica, Min Xu, Ming-Ju Lee
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Patent number: 7659768Abstract: A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.Type: GrantFiled: December 19, 2008Date of Patent: February 9, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Samu Suryanarayana, Arvind Bomdica, Yikai Liang
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Publication number: 20090167405Abstract: A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.Type: ApplicationFiled: December 19, 2008Publication date: July 2, 2009Applicant: Advanced Micro Devices, Inc.Inventors: Samu Suryanarayana, Arvind Bomdica, Yikai Liang