Abstract: A vehicle-mounted controller includes: a GNSS module, an MPU and an MCU. The GNSS module transmits a pulse signal to the MPU via the rigid line and transmits recommended positioning information to the MPU via the serial port line at the moment when a change occurs in high and low levels of the pulse signal; the MPU determines first absolute time according to first reception time when the pulse signal is received, second reception time when the recommended positioning information is received, and the recommended positioning information, and broadcasts the first absolute time to Ethernet network for absolute time synchronization; the MCU determines second absolute time according to time when the pulse signal is received, time when the first absolute time is received, and the recommended positioning information, and broadcasts the second absolute time to a CAN bus for absolute time synchronization.

Abstract: Some embodiments include an encoder to convert a thermometer code into a binary code output information or a Gray code output information. The encoder supports blind input swapping, such that it provides correct output information without prior knowledge of the input swapping. Some embodiments also include a truth table that has additional rows to describe output information when input information at inputs of the encoder is swapped. The encoder includes symmetrical logic functions with respect to information at its inputs as building blocks.

Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.

Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.

Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.

Abstract: Embodiments include apparatuses, methods, and systems including a decision feedback equalizer (DFE). The DFE includes a first summer circuit, a second summer circuit, a decision circuit, and a tap-delay line including a number of delay elements. The first summer circuit is to add together an analog signal and a first set of weighted feedback taps {h(j+1), . . . h(m)} of time delayed signals of a detected symbol to generate a first summand. The second summer circuit is to add together a second set of weighted feedback taps {h(k+1), h(n)} of time delayed signals of the detected symbol to generate a second summand. The decision circuit is to receive at least the first summand and the second summand, to generate the detected symbol based on a sum including the first summand and the second summand. Other embodiments may also be described and claimed.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.