Abstract: An Integrated Circuit includes a target circuit, first and second logic chains, a feedback path and calibration circuitry. The target circuit includes first and second inputs. The first and second logic chains propagate a signal from a common input point to the first and second inputs of the target circuit, respectively. The feedback path receives the signal from the first or second input and feeds the signal back to the common input point. The calibration circuitry is configured to connect the first input to the feedback path thereby forming a first closed-loop oscillator circuit, and measure a first oscillation frequency of the first closed-loop oscillator circuit, connect the second input to the feedback path, thereby forming a second closed-loop oscillator circuit, and measure a second oscillation frequency of the second closed-loop oscillator circuit, and verify a timing constraint responsively to the first and second oscillating frequencies.

Abstract: A system and method for efficient on-chip monitoring of clock signals post-silicon. An electronic circuit includes a post-silicon and on-die signal monitor and a first signal generator that sends a first signal with a first signal period to the signal monitor. The signal monitor selects a first sampling signal with a first sampling period such that a ratio of the first sampling period to the first signal period is greater than one and is a non-integer. The signal monitor selects a reference voltage level for indicating when the first signal is asserted. When the first sampling period has elapsed, the signal monitor samples the first signal to generate a voltage level, and upon completing sampling, determines a duty cycle of the generated voltage levels, which indicates a duty cycle of the first signal. Using a similar approach, the signal monitor is also capable of determining skew between two signals.