Patents by Inventor Yikun Mo

Yikun Mo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11709517
    Abstract: A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: July 25, 2023
    Assignee: NXP USA, Inc.
    Inventors: Jiawei Fu, Jianzhou Wu, Jie Jin, Yikun Mo, Stefano Pietri
  • Patent number: 11689199
    Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 27, 2023
    Assignee: NXP USA, Inc.
    Inventors: Jianluo Chen, Jianzhou Wu, Yikun Mo
  • Patent number: 11588495
    Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: February 21, 2023
    Assignee: NXP USA, Inc.
    Inventors: Stefano Pietri, Michael Todd Berens, Yikun Mo, Ashutosh Jain
  • Publication number: 20220416779
    Abstract: An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 29, 2022
    Inventors: Jianluo Chen, Jianzhou Wu, Yikun Mo
  • Publication number: 20220052707
    Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.
    Type: Application
    Filed: July 12, 2021
    Publication date: February 17, 2022
    Inventors: Stefano Pietri, Michael Todd Berens, Yikun Mo, Ashutosh Jain
  • Publication number: 20210286389
    Abstract: A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 16, 2021
    Inventors: Jiawei Fu, Jianzhou Wu, Jie Jin, Yikun Mo, Stefano Pietri
  • Patent number: 9654091
    Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 16, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jianzhou Wu, Jie Jin, Yikun Mo, Yang Wang
  • Publication number: 20160373102
    Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.
    Type: Application
    Filed: November 20, 2015
    Publication date: December 22, 2016
    Inventors: Jianzhou Wu, Jie Jin, Yikun Mo, Yang Wang