Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: The present invention discloses improved semiconductor device and method for manufacturing wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another portion of the channel region are disposed on a Si epitaxial layer formed on a semiconductor substrate.

Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.

Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.

Abstract: The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and a well region.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Abstract: A transistor and a method for manufacturing the same are disclosed. One cell transistor having silicon-insulator-silicon (“SIS”) structure and two cell transistors having silicon-oxide-nitride-oxide-silicon (“SONOS”) structure constitute the transistor of the present invention which can store 2 bits. The cell transistor having SIS structure and the cell transistors having SONOS structure share one common gate electrode so that the transistor of the present invention requires only one voltage generation and control circuit.

Abstract: The present invention discloses improved semiconductor device and method for manufacturing wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another portion of the channel region are disposed on a Si epitaxial layer formed on a semiconductor substrate.

Abstract: A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.

Abstract: A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.

Abstract: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Abstract: A manufacturing method of semiconductor device of the present invention improves the contact resistance at silicide film while preventing junction region from being damaged, by simple process performed after contact etch. The method comprises a first step for forming an insulating film over a semiconductor substrate having, at least, silicide film at one part and junction region at another part; a second step for selectively etching the insulating film so as to expose both the silicide film and the junction region, in which a side effective film is undesirably formed on the silicide film and a third step for processing by plasma using inert element (e.g. Ar) containing gas in order to remove the side effective film ion the silicide film.