Patents by Inventor Yi-Ling Chen

Yi-Ling Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250132246
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 24, 2025
    Inventors: Yi Ling Liu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250132168
    Abstract: A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.
    Type: Application
    Filed: November 20, 2023
    Publication date: April 24, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ching Chen, Ching-Ling Lin, Wen-An Liang
  • Publication number: 20250125159
    Abstract: A semiconductor device having dismantlable structure is provided. The method includes forming a packaged semiconductor die by mounting the semiconductor die onto a package substrate in a flip chip orientation, attaching an interposer substrate over a backside of the semiconductor die, and encapsulating with an encapsulant the semiconductor die and remaining gap region between the package substrate and the interposer substrate. A bond pad of the semiconductor die is interconnected with a conductive trace of the package substrate. The interposer substrate includes a plurality of conductive pads exposed at a top surface and interconnected with the package substrate. A dismantlable structure is attached on the top surface of the interposer substrate. A first region of the dismantlable structure covers the plurality of conductive pads.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Inventors: Yu Ling Tsai, Yao Jung Chang, Yen-Chih Lin, Tzu Ya Fang, Jian Nian Chen, Yi-Hsuan Tsai
  • Publication number: 20250089364
    Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Inventors: Cheng-Ling WU, Chih-Liang CHEN, Chi-Yu LU, Yi-Yi CHEN, Ting-Yun WU
  • Patent number: 12249158
    Abstract: An object detection method includes steps that are to be performed for each piece of point cloud data received from a lidar module, of selecting a first to-be-combined image from among images received from a camera device that corresponds in time to the piece of point cloud data, selecting a second to-be-combined image from among the images that is the Nth image before the first to-be-combined image in the time order, combining the first to-be-combined image and the second to-be-combined image to generate a combined image, generating a result image by incorporating the piece of point cloud data into the combined image, and inputting the result image into a trained machine learning model in order to determine a class to which each object in the result image belongs.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: March 11, 2025
    Assignee: AUTOMOTIVE RESEARCH & TESTING CENTER
    Inventors: Yun-Ling Chang, Yi-Feng Su, Ying-Ren Chen
  • Publication number: 20250079177
    Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.
    Type: Application
    Filed: November 7, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: En-Ping LIN, Yu-Ling KO, I-Chung WANG, Yi-Jen CHEN, Sheng-Kai JOU, Chih-Teng LIAO
  • Patent number: 12237458
    Abstract: A micro light emitting device display apparatus including a substrate, a plurality of micro light emitting devices, an isolation layer, and at least one first air gap is provided. The substrate has a plurality of connection pads. The micro light emitting devices are discretely disposed on the substrate. The isolation layer is disposed between the substrate and each of the micro light emitting devices. The at least one first air gap is disposed between the substrate and a surface of the isolation layer facing the substrate.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 25, 2025
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Chih-Ling Wu, Yen-Yeh Chen, Yi-Min Su, Yi-Chun Shih
  • Publication number: 20250063805
    Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Yu LIN, Yu-Ling KO, I-Chen CHEN, Chih-Teng LIAO, Yi-Jen CHEN
  • Publication number: 20250062185
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an offset suppression layer is formed on a carrier, a first electronic element and a second electronic element are respectively disposed on the offset suppression layer, and an encapsulant is formed on the offset suppression layer to respectively cover the first electronic element and the second electronic element. The offset suppression layer effectively suppresses or prevents possible offset caused by the encapsulant to the first electronic element and the second electronic element, thereby avoiding yield loss of the semiconductor package.
    Type: Application
    Filed: December 13, 2023
    Publication date: February 20, 2025
    Inventors: Yi-Ling CHEN, Kuan-Wei CHUANG
  • Publication number: 20250038074
    Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: January 30, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12173135
    Abstract: A plasticizer, which is biodegradable, has a molecule including a central structure, at least two connecting structures and at least one side-chain structure. The central structure includes at least one of a benzene derivative and at least one amino acid. The connecting structures are respectively connected to the central structure, wherein the connecting structures include a first connecting structure and a second connecting structure. The first connecting structure is an amine group, and the second connecting structure is a carboxyl group. The side-chain structure is a chain of multiple carbon atoms, and the side-chain structure is connected to at least one of the first connecting structure and the second connecting structure. An amide bond is formed as the side-chain structure connected to the amine group, and an ester bond is formed as the side-chain structure connected to the carboxyl group.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: December 24, 2024
    Assignee: LARGAN MEDICAL CO., LTD.
    Inventors: Wei-Yuan Chen, Tzu-Rong Lu, Yi-Ling Chen, Chun-Hung Teng
  • Publication number: 20240383986
    Abstract: The invention relates to an antibody or antigen binding fragment thereof which is capable of binding to CD1a, which is particularly suitable for treating or preventing one or more inflammatory skin or mucosal disorder, or disease or one or more associated systemic disease or disorder, or one or more inflammatory drug reaction which manifests systemically, or a CD1a-expressing malignancy
    Type: Application
    Filed: May 20, 2022
    Publication date: November 21, 2024
    Inventors: Graham OGG, Clare HARDMAN, Yi-Ling CHEN
  • Publication number: 20240258121
    Abstract: An electronic structure is provided, in which a plurality of conductors are disposed on one surface of an electronic body, an epoxy molding compound is used as a protective layer to encapsulate the plurality of conductors, a circuit portion is bonded onto the other surface of the electronic body, and a plurality of external bumps and solder material are formed on the circuit portion. Therefore, with the design of the protective layer, heat energy can be effectively transferred from the protective layer to the solder material below during a process of heating the electronic structure so as to avoid a problem of non-wetting of the solder material.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 1, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Ling CHEN, Kuan-Wei CHUANG
  • Publication number: 20240167163
    Abstract: An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.
    Type: Application
    Filed: December 23, 2022
    Publication date: May 23, 2024
    Inventors: YI LING CHEN, WEI TSE HO, CHIN-SHENG WANG, PU-JU LIN, CHENG-TA KO
  • Publication number: 20240047420
    Abstract: An electronic package and a manufacturing method thereof are provided, where the manufacturing method is to dispose an electronic structure with a plurality of conductive bumps and a thermal conductor on its upper surface on a carrier structure via external bumps on its lower surface, so that when reflowing the external bumps, the heat of the heat source joint is conducted from the upper surface of the electronic structure to the external bumps on the lower surface via the thermal conductor, so as to facilitate the heating and reflowing of the external bumps to avoid the problem of non-wetting of the solder.
    Type: Application
    Filed: December 8, 2022
    Publication date: February 8, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventor: Yi-Ling CHEN
  • Patent number: 11880985
    Abstract: The disclosure herein enables tracking of multiple objects in a real-time video stream. For each individual frame received from the video stream, a frame type of the frame is determined. Based on the individual frame being an object detection frame type, a set of object proposals is detected in the individual frame, associations between the set of object proposals and a set of object tracks are assigned, and statuses of the set of object tracks are updated based on the assigned associations. Based on the individual frame being an object tracking frame type, single-object tracking is performed on the frame based on each object track of the set of object tracks and the set of object tracks is updated based on the performed single-object tracking. For each frame received, a real-time object location data stream is provided based on the set of object tracks.
    Type: Grant
    Filed: May 28, 2022
    Date of Patent: January 23, 2024
    Assignee: Microsoft Technology Licensing, LLC.
    Inventors: Ishani Chakraborty, Yi-Ling Chen, Lu Yuan
  • Patent number: 11455287
    Abstract: Embodiments are described for a system and method to analyze data at a plurality of data sources. A data analytic workflow may be received. The data analytic workflow may include at least one operation to be performed on a plurality of data sets stored at a plurality of data sources. Instructions may be created based on the operation to be performed and a type of platform that operates the data sources. Furthermore, the instructions may be transmitted to the data sources such that the data sources may execute the operations on the data sets stored at the data sources.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: September 27, 2022
    Assignee: TIBCO Software Inc.
    Inventors: Steven Hillion, Yi-Ling Chen, Zhe Dong, Yong-Sheng Yu, Yong Zhao
  • Publication number: 20220292828
    Abstract: The disclosure herein enables tracking of multiple objects in a real-time video stream. For each individual frame received from the video stream, a frame type of the frame is determined. Based on the individual frame being an object detection frame type, a set of object proposals is detected in the individual frame, associations between the set of object proposals and a set of object tracks are assigned, and statuses of the set of object tracks are updated based on the assigned associations. Based on the individual frame being an object tracking frame type, single-object tracking is performed on the frame based on each object track of the set of object tracks and the set of object tracks is updated based on the performed single-object tracking. For each frame received, a real-time object location data stream is provided based on the set of object tracks.
    Type: Application
    Filed: May 28, 2022
    Publication date: September 15, 2022
    Inventors: Ishani CHAKRABORTY, Yi-Ling CHEN, Lu YUAN
  • Patent number: 11386662
    Abstract: The disclosure herein enables tracking of multiple objects in a real-time video stream. For each individual frame received from the video stream, a frame type of the frame is determined. Based on the individual frame being an object detection frame type, a set of object proposals is detected in the individual frame, associations between the set of object proposals and a set of object tracks are assigned, and statuses of the set of object tracks are updated based on the assigned associations. Based on the individual frame being an object tracking frame type, single-object tracking is performed on the frame based on each object track of the set of object tracks and the set of object tracks is updated based on the performed single-object tracking. For each frame received, a real-time object location data stream is provided based on the set of object tracks.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 12, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishani Chakraborty, Yi-Ling Chen, Lu Yuan
  • Publication number: 20220089691
    Abstract: The present invention relates to anti-SARS-CoV-2 antibodies and/or antigen-binding fragments thereof, which are useful for specific detection of SARS-CoV-2 in a biological sample. The present invention also provides methods and kits for detecting SARS-CoV-2 and methods and compositions for use in diagnosis and treatment of coronavirus disease (COVID-19) using the anti-SARS-CoV-2 antibodies as described herein.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 24, 2022
    Inventors: Szu-Chia LAI, Yu-Yine Huang, Yi-Ling Chen, Jiunn-Jye Wey, Po-Shiuan Hsieh, Meng-Hung Tsai, Jyh-Hwa Kau