Patents by Inventor Yimin Lu

Yimin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11593115
    Abstract: The present disclosure discloses an instruction execution device, a processor including the instruction execution device, a system on chip, and a method for executing a data storage instruction in the processor. The method includes: splitting the data storage instruction into a first split instruction and a second split instruction, wherein the first split instruction is associated with an address operand of the data storage instruction, and the second split instruction is associated with a data operand of the data storage instruction; executing the first split instruction to determine a data storage address corresponding to the address operand; executing the second split instruction to acquire data content corresponding to the data operand; and storing the acquired data content to the determined data storage address in a data storage region. The present disclosure further discloses a corresponding instruction execution device, a processor including the execution device and a system on chip.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 28, 2023
    Assignee: Alibaba Group Holding Limited
    Inventors: Yimin Lu, Xiaoyan Xiang
  • Patent number: 11487680
    Abstract: An apparatus and a method are disclosed. In the apparatus, a memory management unit includes: a first cache unit, adapted to store a plurality of first source operands and one first write address; a second cache unit, adapted to store at least one pair of a second source operand and a second destination address; a write cache module, adapted to discriminate between destination addresses of a plurality of store instructions, so as to store, in the first cache unit, a plurality of source operands corresponding to consecutive destination addresses, and to store, in the second cache unit, non-consecutive destination addresses and source operands corresponding to the non-consecutive destination addresses, where the first write address is an initial address of the consecutive destination addresses; and a bus transmission module, adapted to transmit the plurality of first source operands and the first write address in the first cache unit to a memory through a bus in a write burst transmission mode.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: November 1, 2022
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Xiaoyan Xiang, Yimin Lu, Chaojun Zhao
  • Patent number: 11436146
    Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Yimin Lu, Xiaoyan Xiang, Taotao Zhu, Chaojun Zhao
  • Patent number: 11429391
    Abstract: A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 30, 2022
    Assignee: Alibaba Group Holding LImited
    Inventors: Dongqi Liu, Chang Liu, Yimin Lu, Tao Jiang, Chaojun Zhao
  • Publication number: 20210097009
    Abstract: An apparatus and a method are disclosed. In the apparatus, a memory management unit includes: a first cache unit, adapted to store a plurality of first source operands and one first write address; a second cache unit, adapted to store at least one pair of a second source operand and a second destination address; a write cache module, adapted to discriminate between destination addresses of a plurality of store instructions, so as to store, in the first cache unit, a plurality of source operands corresponding to consecutive destination addresses, and to store, in the second cache unit, non-consecutive destination addresses and source operands corresponding to the non-consecutive destination addresses, where the first write address is an initial address of the consecutive destination addresses; and a bus transmission module, adapted to transmit the plurality of first source operands and the first write address in the first cache unit to a memory through a bus in a write burst transmission mode.
    Type: Application
    Filed: September 10, 2020
    Publication date: April 1, 2021
    Inventors: Xiaoyan XIANG, Yimin LU, Chaojun ZHAO
  • Publication number: 20210089459
    Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.
    Type: Application
    Filed: July 24, 2020
    Publication date: March 25, 2021
    Inventors: Yimin LU, Xiaoyan XIANG, Taotao ZHU, Chaojun ZHAO
  • Publication number: 20210089469
    Abstract: A processor core, a processor, an apparatus, and a method are disclosed. The processor core is coupled to a translation lookaside buffer and a first memory. The processor core further includes a memory processing module that includes: an instruction processing unit, adapted to identify a virtual memory operation instruction and send the virtual memory operation instruction to a bus request transceiver module; the bus request transceiver module, adapted to send the virtual memory operation instruction to an external interconnection unit; a forwarding request transceiver unit, adapted to receive the virtual memory operation instruction broadcast by the interconnection unit and send the virtual memory operation instruction to the virtual memory operation unit; and the virtual memory operation unit, adapted to perform a virtual memory operation according to the virtual memory operation instruction. An initiation core sends the virtual memory operation instruction to the interconnection unit.
    Type: Application
    Filed: July 24, 2020
    Publication date: March 25, 2021
    Inventors: Taotao ZHU, Yimin LU, Xiaoyan XIANG, Chen CHEN
  • Publication number: 20210089318
    Abstract: A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 25, 2021
    Inventors: Dongqi LIU, Chang LIU, Yimin LU, Tao JIANG, Chaojun ZHAO
  • Publication number: 20210089305
    Abstract: Embodiments of the present disclosure provide methods and apparatuses for an instruction executing method. The method can include: receiving an address-unaligned data load instruction, the data load instruction instructing to read target data from a memory; acquiring a first part of data of the target data from a buffer; acquiring a second part of data of the target data from the memory; and merging the first part of data and the second part of data to obtain the target data.
    Type: Application
    Filed: September 22, 2020
    Publication date: March 25, 2021
    Inventors: Yimin LU, Xiaoyan Xiang
  • Publication number: 20200310816
    Abstract: The present disclosure discloses an instruction execution device, a processor including the instruction execution device, a system on chip, and a method for executing a data storage instruction in the processor. The method includes: splitting the data storage instruction into a first split instruction and a second split instruction, wherein the first split instruction is associated with an address operand of the data storage instruction, and the second split instruction is associated with a data operand of the data storage instruction; executing the first split instruction to determine a data storage address corresponding to the address operand; executing the second split instruction to acquire data content corresponding to the data operand; and storing the acquired data content to the determined data storage address in a data storage region. The present disclosure further discloses a corresponding instruction execution device, a processor including the execution device and a system on chip.
    Type: Application
    Filed: March 20, 2020
    Publication date: October 1, 2020
    Inventors: Yimin LU, Xiaoyan XIANG
  • Patent number: 10570262
    Abstract: The present disclosure provides an edible gelatin base film and preparation method thereof, relating to material fields. The preparation method can improve the mechanical property of the film. The films prepared by the method have antibacterial properties, low-temperature stability and high-temperature dissolution, environmental-friendly components. The method includes the following steps: a) preparing gel nanoparticles; b) preparing bacterial cellulose nanoparticles; c) preparing the gelatin base film: mixing pullulan, glycerin, nisin, antibacterial peptide, the gel nanoparticles obtained from step a) and the bacterial cellulose nanoparticles obtained from step b), ultrasonically degassing, then being subjected to coating and drying to obtain the gelatin base film. The preparation method is used to prepare an edible gelatin base film.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: February 25, 2020
    Assignee: NINGXIA JINBOLE FOOD TECHNOLOGY CO., LTD.
    Inventors: Yuzhu Wu, Zheng Li, Yimin Lu
  • Publication number: 20190248971
    Abstract: The present disclosure provides an edible gelatin base film and preparation method thereof, relating to material fields. The preparation method can improve the mechanical property of the film. The films prepared by the method have antibacterial properties, low-temperature stability and high-temperature dissolution, environmental-friendly components. The method includes the following steps: a) preparing gel nanoparticles; b) preparing bacterial cellulose nanoparticles; c) preparing the gelatin base film: mixing pullulan, glycerin, nisin, antibacterial peptide, the gel nanoparticles obtained from step a) and the bacterial cellulose nanoparticles obtained from step b), ultrasonically degassing, then being subjected to coating and drying to obtain the gelatin base film. The preparation method is used to prepare an edible gelatin base film.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Yuzhu Wu, Zheng Li, Yimin Lu