Abstract: A detection apparatus and a server are provided, where the apparatus is configured to detect whether a coolant heat pipe or a solenoid valve on the coolant heat pipe in a device is abnormal, and the apparatus includes a control chip. The control chip can control a working state of the solenoid valve. The control chip can further obtain a temperature of a component in the device. When it is detected whether the coolant heat pipe or the solenoid valve is abnormal, the control chip may obtain a temperature difference of the component in the device when the working state of the solenoid valve is controlled, and relatively conveniently determine whether the coolant heat pipe or the solenoid valve is abnormal based on the temperature difference.

Abstract: A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.

Abstract: A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.

Abstract: The motherboard includes a basic computing unit and an extension unit. The basic computing unit is provided with a basic component and an external interface. The extension unit is configured to extend a function of the basic computing unit. The basic computing unit is coupled to a second external interface of the extension unit through a first external interface on the basic computing unit. A conventional motherboard is split, and a basic computing unit that includes only a processor subsystem and an extension unit that extends input/output and management are formed by properly dividing the processor subsystem and a peripheral system. Impact of an extension component on the basic computing unit is reduced, and the extension component can be flexibly replaced based on an actual requirement.

Abstract: A server power supply includes a first voltage input line, a second voltage input line, a ground cable, a switch, and a voltage limiting device. The switch and the voltage limiting device are connected in series and located between the first voltage input line and the ground cable. When a voltage of the first voltage input line is greater than a conduction voltage, both the switch and the voltage limiting device are in an ON state, so that the server is protected from a relatively high voltage. When the voltage of the first voltage input line decreases and is less than the conduction voltage after the voltage of the first voltage input line is greater than the conduction voltage, the voltage limiting device is in an OFF state.

Abstract: A multi-node server includes a plurality of nodes and a hard disk backplane. Each node includes a power supply module. The power supply module is built in the node. The hard disk backplane is connected to the plurality of nodes through a first connector. The power supply module of each node is connected to a power supply interface of another node through a second connector, where the first connector and the second connector are spaced apart, and air flowing from an air inlet of the multi-node server circulates through a spacing between the first connector and the second connector. A system backplane for connection is not arranged in the multi-node server, but is replaced with the first connector and the second connector with a relatively small volume.

Abstract: A server includes a backplane, and a hard disk in the server may be housed on the backplane. The backplane is disposed between an air exhaust vent and an air intake vent of the server, and the backplane may be parallel to an air inflow direction of the air intake vent or an air outflow direction of the air exhaust vent. The backplane is parallel to the air direction.

Abstract: A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.

Abstract: A detection apparatus and a server are provided, where the apparatus is configured to detect whether a coolant heat pipe or a solenoid valve on the coolant heat pipe in a device is abnormal, and the apparatus includes a control chip. The control chip can control a working state of the solenoid valve. The control chip can further obtain a temperature of a component in the device. When it is detected whether the coolant heat pipe or the solenoid valve is abnormal, the control chip may obtain a temperature difference of the component in the device when the working state of the solenoid valve is controlled, and relatively conveniently determine whether the coolant heat pipe or the solenoid valve is abnormal based on the temperature difference.

Abstract: A packet forwarding method, device, and system for use in non-volatile memory express (NVMe) over fabric are described. According to the method, a first packet sent by a control device is received; a second packet is generated according to the first packet; a network port for forwarding the second packet is selected according to an identity of a target non-volatile memory; and the second packet is encapsulated into a packet that meets an NVMe over fabric forwarding requirement, and the encapsulated second packet is sent by using the selected network port.

Abstract: A packet forwarding method, device, and system for use in non-volatile memory express (NVMe) over fabric. According to the method, a first packet sent by a control device is received; a second packet is generated according to the first packet; a network port for forwarding the second packet is selected according to an identity of a target non-volatile memory; and the second packet is encapsulated into a packet that meets an NVMe over fabric forwarding requirement, and the encapsulated second packet is sent by using the selected network port.

Abstract: A packet forwarding method, device, and system for use in non-volatile memory express (NVMe) over fabric. According to the method, a first packet sent by a control device is received, and an input/output command or a management command that complies with the NVMe protocol and that is included in the first packet is obtained; a second packet is generated according to the input/output command or the management command, where the input/output command or the management command complies with the NVMe protocol and is included in the first packet, and the second packet is a packet for executing the input/output command or the management command; a network port for forwarding the second packet is selected according to an identity of a target non-volatile memory; and the second packet is encapsulated into a packet that meets an NVMe over fabric forwarding requirement, and the encapsulated second packet is sent by using the selected network port.

Abstract: A computer device and a memory startup method of a computer are provided, where a basic input/output system initializes only a first part of memory in a memory initialization phase after a computer is powered on and started, so that an operating system can be started, and after the operating system is started, the basic input/output system continues to initialize memory that is not initialized in the computer, so that, in a startup phase, the computer can start the operating system without needing to wait until all memory has been initialized; therefore, a time from being started to entering the operating system is reduced for the computer, and a user can quickly enter the operating system to perform an operation, thereby improving user experience.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.

Abstract: A packet forwarding method, device, and system for use in non-volatile memory express (NVMe) over fabric. According to the method, a first packet sent by a control device is received, and an input/output command or a management command that complies with the NVMe protocol and that is included in the first packet is obtained; a second packet is generated according to the input/output command or the management command, where the input/output command or the management command complies with the NVMe protocol and is included in the first packet, and the second packet is a packet for executing the input/output command or the management command; a network port for forwarding the second packet is selected according to an identity of a target non-volatile memory; and the second packet is encapsulated into a packet that meets an NVMe over fabric forwarding requirement, and the encapsulated second packet is sent by using the selected network port.

Abstract: A computer device and a memory startup method of a computer are provided, where a basic input/output system initializes only a first part of memory in a memory initialization phase after a computer is powered on and started, so that an operating system can be started, and after the operating system is started, the basic input/output system continues to initialize memory that is not initialized in the computer, so that, in a startup phase, the computer can start the operating system without needing to wait until all memory has been initialized; therefore, a time from being started to entering the operating system is reduced for the computer, and a user can quickly enter the operating system to perform an operation, thereby improving user experience.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing. A reliable TLP transmission module is configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time. A destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC. Thereby, reliable transmission of a TLP is implemented in a case of a PCIE switching dual-plane networking connection.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing. A reliable TLP transmission module is configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time. A destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC. Thereby, reliable transmission of a TLP is implemented in a case of a PCIE switching dual-plane networking connection.