Abstract: A method for qualitative identification and quantitative determination of caffeine in a drug. In the method, terahertz absorption coefficient spectra of drugs with different concentrations of caffeine are measured, from which the frequency points, amplitudes and peak areas of characteristic peaks of the drugs with different concentrations of caffeine are obtained as characteristic quantities. Concentration gradients are established between the concentrations and the characteristic quantities, respectively. The characteristic quantities are imported to the SVR model to establish a training set and a test set. Finally, the qualitative identification and quantitative analysis of caffeine in unknown drugs are achieved.

Abstract: A semiconductor structure and a method for forming the same, and a memory and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate, in which a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form grooves which divide the active layer and the sacrificial layer into a plurality of active areas; filling the grooves to form a first isolation layer surrounding the active areas; patterning the active layer in the active areas to form a plurality of separate active patterns; removing the sacrificial layer via openings between adjacent active patterns to form gaps between bottoms of the active patterns and the substrate; forming bit lines in the gaps; and forming semiconductor pillars on partial tops of the active patterns.

Abstract: Disclosed are an advanced persistent threat (APT) detection method and system based on a continuous-time dynamic heterogeneous graph network (CDHGN). The method includes: selecting network interaction event data, extracting entities from the network interaction event data as source nodes and target nodes, extracting an interaction event occurring between a source node and a target node as an edge, and determining a type and an attribute of a node, a type and an attribute of the edge, and a moment at which an interaction event occurs, to obtain a continuous-time dynamic heterogeneous graph; converting each type of edge in the continuous-time dynamic heterogeneous graph into a vector by a CDHGN encoder, to obtain an embedding representation by a CDHGN decoder to obtain a detection result of whether each type of edge is an abnormal edge, to intercept an APT attack.

Abstract: A semiconductor structure comprises: a substrate; a first transistor including a first gate located in the substrate and a first terminal located on a surface of the substrate, the first terminal being configured to be connected to a first-type memory cell; and a second transistor including a second gate located in the substrate and a second terminal located on the surface of the substrate, the second terminal being configured to be connected to a second-type memory cell, and a width of the second gate being less than a width of the first gate.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, where a sacrificial layer and an active layer located on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form a groove, where the active layer and the sacrificial layer are divided into a plurality of active regions by the groove; forming a first isolation layer surrounding the active regions in the groove; patterning the active layer in the active regions to form a plurality of separate active patterns, where at least one of side walls or ends of the active patterns is connected to the first isolation layer; removing the sacrificial layer along an opening located between two adjacent one of the active patterns to form a gap between a bottom of the active patterns and the semiconductor substrate; and forming a bit line in the gap.

Abstract: The present invention relates to a semiconductor structure and its forming method, and a memory and its forming method. The semiconductor structure includes a substrate, a vertical transistor on the substrate, and a bit line connected to the bottom of the vertical transistor and disposed between the bottom of the vertical transistor and the substrate. The vertical transistor in such a semiconductor structure has a relatively small plane dimension.

Abstract: A method for forming the semiconductor structure includes: providing a substrate, forming a sacrificial layer and an active layer on the sacrificial layer on the substrate; etching the active layer and the sacrificial layer to form active lines extending along a first direction; forming a first isolation layer that fills a spacing between the active lines; etching ends of the active lines to form openings, and exposing the sacrificial layer on side walls of the openings; removing the sacrificial layer along the openings, and forming gap between a bottom of the active lines and the substrate; and filling the gaps with a conductive material to form bit lines extending along the first direction.

Abstract: The present invention relates to a semiconductor structure and a method for forming the same, and a memory and a method for forming the same. The method for forming the semiconductor structure includes: providing a substrate on which a sacrificial layer and an active layer located on the sacrificial layer are formed; patterning the active layer to form several discrete active pillars; removing the sacrificial layer to form a gap; forming a bit line within the gap; and forming a semiconductor pillar on the top of the active pillar. The above method can reduce the planar size of the transistor and increase the storage density of the memory.

Abstract: The present invention discloses a topological preserving deformation method for a 3D model based on a multiple volumetric harmonic field, and belongs to the fields of computer graphics, computational mathematics, topology and differential geometry. Firstly, a tetrahedral mesh is constructed between a source 3D model and a target 3D model; then, a domain of topological transformation in a deformation process is calculated based on a traditional single volumetric harmonic field; special multiple boundary conditions are set; next, a multiple volumetric harmonic field is calculated; and finally, topological preserving surface deformation is induced.

Abstract: The present application relates to a semiconductor structure and its forming method. The semiconductor structure comprises a substrate; a first transistor, including a first channel region disposed within the substrate, and a first end disposed at surface of the substrate, the first end being adapted to connect with a first-type storage cell; and a second transistor, including a second channel region disposed within the substrate, and a second end disposed at surface of the substrate, the second end being adapted to connect with a second-type storage cell, the first channel region and the second channel region having different areas.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.

Abstract: Disclosed are a method and system for detecting a complex multi-step attack in an electric power system. The method includes: collecting interaction behavior data of a network entity; preprocessing the interaction behavior data of the network entity based on a heterogeneous graph to obtain input data; and inputting the input data into a complex multi-step attack detection module to obtain an attack detection result. Information is extracted from the interaction behavior data to construct a node and an edge of the heterogeneous graph. Timestamp information of a destination node and an adjacent source node of the destination node is input into a Time2Vec layer to obtain a first time embedding representation. Data that fuses node feature information and the first time embedding representation is input into a Heteformer layer, and a second node embedding representation is obtained as input data and input into the complex multi-step attack detection module.

Abstract: The present application relates to a semiconductor structure and its forming method. The semiconductor structure comprises a substrate; a first transistor that includes a first channel disposed within the substrate, and a first end disposed at surface of the substrate, the first end being adapted to connect with a first-type storage cell; a second transistor that includes a second channel disposed within the substrate, and a second end disposed at surface of the substrate, the second end being adapted to connect with a second-type storage cell, the second channel having a length greater than length of the first channel. The present application enables fabrication techniques of the first transistor and the second transistor compatible. Moreover, the present application is conducive to enhancing integration density of the storage cells of the first transistor and/or the second transistor in the memory lays foundation for enlarging the fields of application of the memory.

Abstract: Disclosed are an active metal brazing paste composition, a brazing paste and a method for brazing ceramics and metals. The composition includes a binder and metal powder. The metal powder includes active metal brazing powder and brazing-aid metal powder. The brazing-aid metal powder contains copper powder and/or copper-silver alloy powder. The active metal brazing powder is alloy powder containing copper, silver, and an active metal. With the total weight of the metal powder as a reference, the content of the active metal is 1.5 wt % or more, the content of silver is 40 wt % to 90 wt %, and the content of oxygen is 0.5 wt % or less.

Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate; a semiconductor pillar located on the substrate and a gate pillar located on the semiconductor pillar, in which the semiconductor pillar and the gate pillar both extend in a direction perpendicular to a plane of the substrate; a first word line extending in a first direction parallel to the plane of the substrate and surrounding the semiconductor pillar; and a semiconductor layer located above the semiconductor pillar and at least surrounding a sidewall of the gate pillar.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, a sacrificial layer and active layer on sacrificial layer being formed on the substrate; etching the active layer and sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along first direction; filling an opening located between two adjacent ones of active lines to form a first isolating layer; etching an end of active lines to form an opening hole; removing sacrificial layer along opening hole, to form a gap between a bottom of the active lines and substrate; filling a conductive material in the gap to form a bit line extending along first direction; patterning the active lines to form a plurality of separate active pillars arrayed along first direction and second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars.

Abstract: The present invention provides a semiconductor manufacturing method. A substrate having a plurality of first trenches can be provided. The substrate can include a first pattern formed between two adjacent first trenches. A first dielectric layer can be deposited onto the substrate. The first dielectric layer can cover at least one side wall of the first pattern. A second dielectric layer can be deposited onto the substrate. The second dielectric layer can fill the first trenches. The first pattern can be severed to form a second pattern on the substrate. The second dielectric layer can be removed from the first trenches.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.

Abstract: The present invention discloses a boundary layer mesh generation method based on an anisotropic volume harmonic field, and belongs to the technical filed of computational fluid dynamics, numerical simulation, computer aided design and manufacturing. First, a boundary surface mesh of the Minkowski sum is used to construct a tetrahedral background mesh required for solving volume harmonic fields, then an anisotropic tensor is automatically added according to the actual demand, the anisotropic volume harmonic field is calculated under the control of the tensor, and finally, the advancing direction required by the boundary layer mesh is generated in combination with special weighted Laplace smoothing.

Abstract: A display driving device and a display driving method with low power consumption are disclosed. The display driving device with low power consumption includes a source driving circuit, a display content detection circuit and a display timing driving circuit. Pixel switches are disposed between an output terminal of source driving circuit and sub-pixels of panel. The display timing driving circuit is coupled to the source driving circuit and display content detection circuit and used to change driving order according to display information detected by the display content detection circuit to control turn-on times of at least two pixel-switches of the pixel-switches to overlap each other to simultaneously drive at least two sub-pixels of the sub-pixels corresponding to the at least two pixel-switches.