Patents by Inventor Yin-Chieh Liao

Yin-Chieh Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12166054
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20240387587
    Abstract: A semiconductor image sensor includes a first substrate including a first front side and a first back side, and a second substrate including a second front side and a second back side. The first substrate includes a layer and a first light-sensing element in the layer. The layer includes a first semiconductor material, and the first light-sensing element includes a second semiconductor material. The second substrate is bonded to the first substrate with the second front side facing the first back side.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: JHY-JYI SZE, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, SIN-YI JIANG, KUAN-CHIEH HUANG
  • Publication number: 20240387766
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Patent number: 12148853
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Publication number: 20240372028
    Abstract: A method of manufacturing a semiconductor structure includes: forming a light-absorption layer in a substrate, wherein the light-absorption layer includes an upper surface above an upper surface of the substrate; forming a first doped region and a second doped region in the light-absorption layer adjacent to the first doped region; depositing a first patterned mask layer over the light-absorption layer, wherein the first patterned mask layer includes an opening exposing the second doped region and covers the first doped region; forming a first silicide layer in the opening on the second doped region; and forming a second silicide layer on the first doped region.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: YI-SHIN CHU, HSIANG-LIN CHEN, YIN-KAI LIAO, SIN-YI JIANG, KUAN-CHIEH HUANG
  • Patent number: 12125934
    Abstract: A method of manufacturing a semiconductor structure includes: forming a light-absorption layer in a substrate; forming a first doped region of a first conductivity type and a second doped region of a second conductivity type in the light-absorption layer adjacent to the first doped region; depositing a first patterned mask layer over the light-absorption layer, wherein the first patterned mask layer includes an opening exposing the second doped region and covers the first doped region; forming a first silicide layer in the opening on the second doped region; depositing a barrier layer over the first doped region; and annealing the barrier layer to form a second silicide layer on the first doped region.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Shin Chu, Hsiang-Lin Chen, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang
  • Publication number: 20240339555
    Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Yin-Kai Liao, Jen-Cheng Liu, Kuan-Chieh Huang, Chih-Ming Hung, Yi-Shin Chu, Hsiang-Lin Chen, Sin-Yi Jiang
  • Patent number: 5013224
    Abstract: A fan assembly includes a statonary support holding a rotary support operated by a motor for turning 360 degrees about a vertical axis and a plurality of fan units mounted on the rotary support. First conductors are provided to connect the motor and the fan units to rotary conducting plates which respectively contact stationary second conducting plates, and second conductors are connected to the second conducting plates, thereby preventing the conductors of the assembly from becoming tangled.
    Type: Grant
    Filed: December 7, 1989
    Date of Patent: May 7, 1991
    Inventor: Yin-Chieh Liao
  • Patent number: D335703
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: May 18, 1993
    Inventor: Yin-Chieh Liao