Abstract: Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

Abstract: A method of correcting a configuration memory frame may include identifying an erroneous memory frame in a plurality of memory frames in the integrated circuit. The erroneous memory frame may be identified with error detection circuitry on the integrated circuit. A portion of data stored in an off-chip memory module may be read with controller circuitry. The read data portion may correspond to the erroneous memory frame. The erroneous memory frame may thus be corrected by loading the read data portion into the erroneous memory frame during normal operation of the integrated circuit. Every memory bit in the erroneous memory frame may be replaced or overwritten when the read data portion is loaded into the erroneous memory frame. The integrated circuit may be partially reconfigured when the erroneous memory frame is corrected.

Abstract: Methods for partial reconfiguration compatibility detection in an integrated circuit device are disclosed. A disclosed method includes storing a unique identifier that identifies a partial reconfiguration region of the integrated circuit device in a storage circuit. A control circuit may receive an input partial reconfiguration data that activates the operations of the partial reconfiguration region. The method further includes comparing the input partial reconfiguration data to the stored unique identifier prior to activating the operations of the partial reconfiguration region of the integrated circuit device. The input partial reconfiguration data may contain an associated identifier that is derived from the unique identifier during a design compilation operation of the integrated circuit device.

Abstract: Techniques for compiling an integrated circuit (IC) design with a computer-aided design tool are provided. The IC design may include multiple dynamic configuration regions that may be updated during runtime without affecting other regions on the IC device. When an IC design is compiled for an IC device, dynamic configuration regions in the IC design are identified. The computer-aided design tool may generate a partial configuration file for each identified dynamic configuration region. Two or more partial reconfiguration files may be combined to obtain a single partial configuration file that may then be used to configure respective dynamic configuration regions on the IC device.

Abstract: An integrated circuit (IC) that enables a fast parallel-to-serial memory data transfer is described. The IC includes a first input output (IO) interface operable to receive a plurality of data in parallel from a memory device, wherein the plurality of data is a binary sequence. The IC also includes a controller receiving the plurality of data from the first IO interface, wherein the controller is operable to generate a compressed data by compressing the plurality of data, wherein a portion of the compressed data provides information on a significant portion of the plurality of data. And the IC also includes a second IO interface receives the compressed data from the controller and serially shifts the compressed data out of the IC.

Abstract: Methods and apparatuses for managing unusable blocks in a memory module are provided. The memory table may include a plurality of unusable block addresses in the memory module where the plurality of unusable block addresses is arranged in a sequential order in the memory table. A number of unusable blocks in the memory module is identified by reading a word that represents the number of unusable blocks from the memory table. A first pair of addresses comprises a first unusable block address and a first corresponding mapped memory address. The pair of addresses are read from the memory table and stored in a storage element of a controller. Only a single pair of addresses is stored in the storage element of the controller at any one time according to one embodiment.

Abstract: A method of compressing data is provided. In one implementation, the method includes compressing data with a plurality of compression schemes, where the compressing is computer implemented. Also, in one implementation, the plurality of compression schemes include a first compression scheme and a second compression scheme and the compressing includes compressing a first portion of the data with the first compression scheme and compressing a second portion of the data with the second compression scheme, where the second compression scheme is different from the first compression scheme. In one implementation, the method further includes determining a suitable compression scheme from the plurality of compression schemes with which to compress each portion of the data, where the determining is computer implemented. In one implementation, the data is configuration data for configuring an IC.