Abstract: The present invention provides a preparation method of a battery composite material, wherein a precursor with the chemical formula FePO4 is formed by introducing air or oxygen during calcination. The precursor is then reacted with a first reactant containing lithium atoms and a carbon source to form a battery composite material with the chemical formula LiFePO4.

Abstract: Systems and methods are provided for identifying one or more portions of images or video frames that are appropriate for augmented overlay of advertisement or other visual content, and augmenting the image or video data to include such additional visual content. Identifying the portions appropriate for overlay or augmentation may include employing one or more machine learning models configured to identify objects or regions of an image or video frame that meet criteria for visual augmentation. The pose of the augmented content presented within the image or video frame may correspond to the pose of one or more real-world objects in the real world scene captured within the original image or video.

Abstract: The present application discloses a method for producing piperonal by using a recombinant engineered bacterium co-expressing trans-anethole oxygenase and formate dehydrogenase, and an engineered bacterium thereof, including constructing a formate dehydrogenase gene fdh and trans-anethole oxygenase gene tao or trans-anethole oxygenase mutant gene co-expression recombinant vector; inductively expressing recombinant genetically engineered bacterium; and producing piperonal by using the recombinant genetically engineered bacterium. 15.91 g/L of piperonal with a transformation rate of 79.55% and a time-space transformation rate of 2.27 g/L/h can be finally obtained during catalysis, and the yield is significantly improved compared with the existing piperonal, thereby being more conducive to the smooth realization of industrial production.

Abstract: An apparatus for performing decision feedback equalizer (DFE) adaptation control is provided. The apparatus includes arithmetic circuits, slicers, sample and hold circuits, a phase detector and a control circuit for related operations. The control circuit generates parameters at least according to an error sample value and data sample values, and dynamically updates the parameters based on at least one predetermined rule to perform the DFE adaptation control. The parameters include a first parameter, another parameter and a factor adjustment parameter. Regarding at least one data pattern, the control circuit selectively replaces the error sample value with a predetermined value according to whether a temporary storage value of the error sample value conforms to a predetermined condition to control the other parameter and the first parameter, in order to prevent triggering an unstable effect and thereby prevent abnormal operations.

Abstract: The present invention relates to an improved method of producing a transgenic plant. Said method comprises, inter alia, the steps of a) providing a wounded transformable explant comprising a hypocotyl or a portion thereof, at least one cotyledon and wounded tissue, b) transforming cells comprised by said explant, and c) transferring said explant to a growing medium, comprising at least one selection compound for a selectable marker, by inserting the hypocotyl of said explant into said growing medium. Moreover, the present invention relates to a plant obtainable by the method according to the present invention.

Abstract: The present application discloses a method for producing piperonal by using a recombinant engineered bacterium co-expressing trans-anethole oxygenase and formate dehydrogenase, and an engineered bacterium thereof, including constructing a formate dehydrogenase gene fdh and trans-anethole oxygenase gene tao or trans-anethole oxygenase mutant gene co-expression recombinant vector; inductively expressing recombinant genetically engineered bacterium; and producing piperonal by using the recombinant genetically engineered bacterium. 15.91 g/L of piperonal with a transformation rate of 79.55% and a time-space transformation rate of 2.27 g/L/h can be finally obtained during catalysis, and the yield is significantly improved compared with the existing piperonal, thereby being more conducive to the smooth realization of industrial production.

Abstract: Systems and methods are provided for identifying one or more portions of images or video frames that are appropriate for augmented overlay of advertisement or other visual content, and augmenting the image or video data to include such additional visual content. Identifying the portions appropriate for overlay or augmentation may include employing one or more machine learning models configured to identify objects or regions of an image or video frame that meet criteria for visual augmentation. The pose of the augmented content presented within the image or video frame may correspond to the pose of one or more real-world objects in the real world scene captured within the original image or video.

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.

Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof are provided. A deep well region is disposed in a substrate. An isolation structure is disposed in the substrate to define a first active area and a second active area. A well region is disposed in the deep well region in the first active area. A gate is disposed on the substrate in the first active area. A gate dielectric layer is disposed between the gate and the substrate. A first doped region is disposed in the well region in the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structure is disposed on the isolation structure, surrounds the second doped region and is connected to the gate.

Abstract: A dome-shaped push switch includes a sheet and a conducting layer disposed at a low surface of the sheet. The sheet has a pressing portion arching upward. The conducting layer is disposed at a lower surface of the sheet. The conductivity of the sheet is greater than that of the sheet. The pressing portion includes at least one through hole penetrating through the pressing portion. The through hole has a side wall, the side wall sequentially has a shear surface and a tear surface from bottom up, and a fillet is provided between the shear surface and a lower surface of the pressing portion.

Abstract: A dome-shaped push switch includes a sheet and a conducting layer disposed at a low surface of the sheet. The sheet has a pressing portion arching upward. The conducting layer is disposed at a lower surface of the sheet. The conductivity of the sheet is greater than that of the sheet. The pressing portion includes at least one through hole penetrating through the pressing portion. The through hole has a side wall, the side wall sequentially has a shear surface and a tear surface from bottom up, and a fillet is provided between the shear surface and a lower surface of the pressing portion.

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.

Abstract: An input device may include various sensor electrodes that detect positional information of an input object in a sensing region of the input device. The input device may include a first sensor electrode that detects a first change in a first variable capacitance in response to a deflection of a conductive layer by the input object. The input device may include a second sensor electrode that detects a second change in a second variable capacitance in response to the deflection of the conductive layer by the input object. The first change in the first variable capacitance and the second change in the second variable capacitance may determine an acquired force image of the input force. An adjusted force image may be determined from the acquired force image using the positional information.

Abstract: A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well.

Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.