Patents by Inventor Yin Guo
Yin Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960521Abstract: The present disclosure discloses a text classification system based on feature selection and a method thereof in the technical field of natural language processing and short text classification, comprising: acquiring a text classification data set; dividing the text classification data set into a training text set and a test text set, and then pre-processing the training text set and the test text set; extracting feature entries from the pre-processed training text set through improved chi-square statistics to form feature subsets; using TF-IWF algorithm to give the weight to the extracted feature entries; based on the weighted feature entries, establishing a short text classification model based on a support vector machine; and classifying the pre-processed test text set by the short text classification model. The present disclosure solves the problem that the short text content is sparse to some extent, thereby improving the performance of short text classification.Type: GrantFiled: January 16, 2023Date of Patent: April 16, 2024Inventors: Yin Lu, Qingyuan Li, Abdusamjan Abdukirim, Jie Hu, Luocheng Wu, Yongan Guo
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Patent number: 11942503Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.Type: GrantFiled: May 8, 2019Date of Patent: March 26, 2024Assignee: EASTERN BLUE TECHNOLOGIES, INC.Inventors: Jianjun Guo, Yin Qian
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Patent number: 11926660Abstract: The present disclosure encompasses compositions and methods for effectively treating at least one symptom or sign of Aß plaque or cerebral amyloid angiopathy (CAA) associated symptoms, or for decreasing amyloid plaque load or CAA load. The method comprises administering an effective amount of an anti-ApoE antibody to a mammalian subject, such as to a human.Type: GrantFiled: August 24, 2021Date of Patent: March 12, 2024Assignee: Washington UniversityInventors: David Holtzman, Hong Jiang, Thu Nga Bien-Ly, Mark S. Dennis, Jing Guo, Adam P. Silverman, Ryan J. Watts, Yin Zhang
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Publication number: 20220332862Abstract: The invention relates to a poly[?-cyanoacrylate] hydrolyzate, a preparation method and an application thereof, belonging to the field of pharmaceutical and chemical industry. A main technical solution is as follows: provided is a poly[?-cyanoacrylate] hydrolyzate having a chemical formula: CH2—CRCOOHn, wherein R=—CN or —COOH. Poly[2-cyanoacrylic acid] provided by the present invention is dispersed in water to prepare the negatively charged microsphere, that is, to obtain the new blank embolic microsphere, the particle size of the microsphere can be adjusted in a micron-scale range, and the microsphere have a deformation function to pass through a vascular with a specific shape, which can tightly embolize the vascular to avoid ectopic embolism caused by falling off; poly[2-carboxyacrylic acid] can be used for preparing a new nano-drug carrier, improving the curative effect of the carried drug on diseased tissues and reduce the toxic and side effects of the carried drug on normal tissues.Type: ApplicationFiled: August 21, 2020Publication date: October 20, 2022Inventors: Junping WANG, Yin GUO
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Patent number: 10862490Abstract: A calibration circuit for body biasing includes a phase detector, first and second voltage generators, and first and second voltage regulators. The phase detector has an input terminal configured to receive an oscillation signal from a ring oscillator. The phase detector provides output signals indicative of phase differences between the oscillation signal and a reference signal. The first voltage generator provides a first reference voltage using the output signals from the phase detector, and the first voltage regulator provides a first biasing voltage using the first reference voltage. The second voltage generator provides a second reference voltage using the first reference voltage, and the second voltage regulator provides a second biasing voltage using the second reference voltage. The first biasing voltage is used to bias P-wells of transistors in the ring oscillator, and the second biasing voltage is used to bias N-wells of transistors in the ring oscillator.Type: GrantFiled: June 12, 2019Date of Patent: December 8, 2020Assignee: NXP USA, Inc.Inventors: Xiaolei Wu, Yin Guo, Haitian Zhou
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Publication number: 20200044627Abstract: A calibration circuit for body biasing includes a phase detector, first and second voltage generators, and first and second voltage regulators. The phase detector has an input terminal configured to receive an oscillation signal from a ring oscillator. The phase detector provides output signals indicative of phase differences between the oscillation signal and a reference signal. The first voltage generator provides a first reference voltage using the output signals from the phase detector, and the first voltage regulator provides a first biasing voltage using the first reference voltage. The second voltage generator provides a second reference voltage using the first reference voltage, and the second voltage regulator provides a second biasing voltage using the second reference voltage. The first biasing voltage is used to bias P-wells of transistors in the ring oscillator, and the second biasing voltage is used to bias N-wells of transistors in the ring oscillator.Type: ApplicationFiled: June 12, 2019Publication date: February 6, 2020Inventors: Xiaolei Wu, Yin Guo, Haitian Zhou
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Patent number: 9946597Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.Type: GrantFiled: September 4, 2016Date of Patent: April 17, 2018Assignee: NXP USA, INC.Inventors: Zhihong Cheng, Yin Guo
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Patent number: 9726724Abstract: An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.Type: GrantFiled: November 26, 2014Date of Patent: August 8, 2017Assignee: NXP USA, INC.Inventors: Xiuqiang Xu, Yin Guo, Shayan Zhang, Wanggen Zhang, Xu Zhang, Yizhong Zhang
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Publication number: 20170139772Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.Type: ApplicationFiled: September 4, 2016Publication date: May 18, 2017Inventors: Zhihong Cheng, Yin Guo
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Publication number: 20150323590Abstract: An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.Type: ApplicationFiled: November 26, 2014Publication date: November 12, 2015Inventors: Xiuqiang Xu, Yin Guo, Shayan Zhang, Wanggen Zhang, Xu Zhang, Yizhong Zhang
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Patent number: 8904333Abstract: A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.Type: GrantFiled: April 19, 2013Date of Patent: December 2, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Haifeng Bai, Yin Guo, Xuewen He, Kun Wu, Lei Zhang, Shayan Zhang
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Publication number: 20140284092Abstract: An electronic device such as a circuit board has a contact pad for connection to a contact of a component, and a pad portion interconnection. The contact pad has physically separate pad portions. The pad portion interconnection electrically connects the pad portions of the contact pad, independently of any mounted connection on the pad portions. Providing multiple pad portions for a single contact pad allows the contact pad to function even if one of the pad portions is damaged such as by peeling off. An example application is an EMC (Electromagnetic Compatibility) and/or ESD (Electro-Static Discharge) test circuit board.Type: ApplicationFiled: February 12, 2014Publication date: September 25, 2014Inventors: Jing Bai, Yin Guo, Shayan Zhang, Yanyan Zhang
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Publication number: 20140109029Abstract: A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.Type: ApplicationFiled: April 19, 2013Publication date: April 17, 2014Inventors: Haifeng Bai, Yin Guo, Xuewen He, Kun Wu, Lei Zhang, Shayan Zhang
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Patent number: 8643426Abstract: A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation.Type: GrantFiled: September 6, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Wenzhong Zhang, Yin Guo, Shayan Zhang
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Publication number: 20130222037Abstract: A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation.Type: ApplicationFiled: September 6, 2012Publication date: August 29, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Wenzhong Zhang, Yin Guo, Shayan Zhang