Abstract: The invention relates to a poly[?-cyanoacrylate] hydrolyzate, a preparation method and an application thereof, belonging to the field of pharmaceutical and chemical industry. A main technical solution is as follows: provided is a poly[?-cyanoacrylate] hydrolyzate having a chemical formula: CH2—CRCOOHn, wherein R=—CN or —COOH. Poly[2-cyanoacrylic acid] provided by the present invention is dispersed in water to prepare the negatively charged microsphere, that is, to obtain the new blank embolic microsphere, the particle size of the microsphere can be adjusted in a micron-scale range, and the microsphere have a deformation function to pass through a vascular with a specific shape, which can tightly embolize the vascular to avoid ectopic embolism caused by falling off; poly[2-carboxyacrylic acid] can be used for preparing a new nano-drug carrier, improving the curative effect of the carried drug on diseased tissues and reduce the toxic and side effects of the carried drug on normal tissues.

Abstract: A calibration circuit for body biasing includes a phase detector, first and second voltage generators, and first and second voltage regulators. The phase detector has an input terminal configured to receive an oscillation signal from a ring oscillator. The phase detector provides output signals indicative of phase differences between the oscillation signal and a reference signal. The first voltage generator provides a first reference voltage using the output signals from the phase detector, and the first voltage regulator provides a first biasing voltage using the first reference voltage. The second voltage generator provides a second reference voltage using the first reference voltage, and the second voltage regulator provides a second biasing voltage using the second reference voltage. The first biasing voltage is used to bias P-wells of transistors in the ring oscillator, and the second biasing voltage is used to bias N-wells of transistors in the ring oscillator.

Abstract: A calibration circuit for body biasing includes a phase detector, first and second voltage generators, and first and second voltage regulators. The phase detector has an input terminal configured to receive an oscillation signal from a ring oscillator. The phase detector provides output signals indicative of phase differences between the oscillation signal and a reference signal. The first voltage generator provides a first reference voltage using the output signals from the phase detector, and the first voltage regulator provides a first biasing voltage using the first reference voltage. The second voltage generator provides a second reference voltage using the first reference voltage, and the second voltage regulator provides a second biasing voltage using the second reference voltage. The first biasing voltage is used to bias P-wells of transistors in the ring oscillator, and the second biasing voltage is used to bias N-wells of transistors in the ring oscillator.

Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.

Abstract: An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

Abstract: Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.

Abstract: An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

Abstract: A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.

Abstract: An electronic device such as a circuit board has a contact pad for connection to a contact of a component, and a pad portion interconnection. The contact pad has physically separate pad portions. The pad portion interconnection electrically connects the pad portions of the contact pad, independently of any mounted connection on the pad portions. Providing multiple pad portions for a single contact pad allows the contact pad to function even if one of the pad portions is damaged such as by peeling off. An example application is an EMC (Electromagnetic Compatibility) and/or ESD (Electro-Static Discharge) test circuit board.

Abstract: A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.

Abstract: A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation.

Abstract: A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation.