Patents by Inventor Yin Hao

Yin Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254911
    Abstract: A semiconductor device includes a FEOL structure and a transistor. The transistor is disposed on the FEOL structure and includes a back gate, an active channel layer, an electrode, a dielectric layer and a first blocking layer. The back gate is disposed on the FEOL structure. The active channel layer is disposed on the back gate. The electrode electrically is connected to the active channel layer. The dielectric layer is disposed over the active channel layer. The first blocking layer is disposed on the dielectric layer and overlaps the active channel layer.
    Type: Application
    Filed: February 5, 2024
    Publication date: August 7, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Wei TSAI, Yan-Yi CHEN, Yin-Hao WU, Hai-Ching CHEN
  • Publication number: 20250167343
    Abstract: The present application relates to a battery and an electronic device. The battery includes a first shell, a second shell, and a battery core. The first shell provides a receiving cavity. The battery core is disposed in the receiving cavity. The second shell is disposed on a side of the battery core away from the first shell, and the second shell is connected to the first shell. A support structure is provided at an outer surface of the second shell away from the battery core. The support structure is provided protruding from the outer surface of the second shell, and heat dissipation channels are formed between the support structure and the outer surface of the second shell.
    Type: Application
    Filed: November 15, 2024
    Publication date: May 22, 2025
    Inventors: JONG-RU RAU, Yin-Hao Lo, Chung-Chun Lin, Yu-Hao Fang, Yu-Fan Su, Yang-Chuan Tsai, Yu-Ti Sha, Guan-Zhen Gu
  • Publication number: 20250113841
    Abstract: The use of Black Solider Fly Larvae as Palatant/Palatability Enhancer for use in edible pet products This invention disclosed a palatability enhancer for edible pet products using black solider fly (Hermetia illucens) larvae, wherein the black solider fly larvae are collected following the commercial farming, the greater part of the materials being processed for safety and size reduced as necessary, at 10.0%-80.0%. The palatability enhancer may also include at least one of the following: Cysteine, Arginine, Alanine, Glutamine, Aspartic acid, Glycine, Phenylalanine, Isoleucine, Histidine, Vitamin B1, and a reducing sugar, at 0.1%-10.0% by weight.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Lingxiang Sun, Steven Ho, Xiaoming Liu, Ricardo Martinez, Yin-Hao Chen
  • Publication number: 20240250133
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a dielectric layer, a source electrode, and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the dielectric layer is disposed on a side of the active layer, and the source electrode and the drain electrode pass through the dielectric layer to electrically connect with the active layer, wherein a first contact surface is formed between the source electrode and the active layer, a second contact surface is formed between the drain electrode and the active layer, the first contact surface and the second contact surface are subjected to a plasma treatment or a deposition treatment to form a protective interface layer.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Wei TSAI, Chi-Min CHEN, Yin-Hao WU, Kai-Wen CHENG, Hai-Ching CHEN, Yu-Ming LIN, Chung-Te LIN
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11830589
    Abstract: The disclosure provides a disease classification method and a disease classification device. The disease classification method includes: inputting samples into a first stage model and obtaining a first stage determination result; inputting first samples determined positive by the first stage model into a second stage high specificity model to obtain second samples determined to be positive and third samples determined to be negative and rule in the second samples; inputting fourth samples determined negative by the first stage model into a second stage high sensitivity model to obtain fifth samples determined to be positive and sixth samples determined to be negative and rule out the sixth samples; obtaining a second stage determination result of the second and sixth samples; and inputting the third and fifth samples not ruled in or ruled out into a third stage model and obtaining a third stage determination result of the third and fifth samples.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 28, 2023
    Assignees: Acer Incorporated, Acer Medical Inc., Taipei Veterans General Hospital
    Inventors: Jun-Hong Chen, Tsung-Hsien Tsai, Chun-Hsien Li, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
  • Patent number: 11545619
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Hsiang Wang, Han-Ting Lin, Yu-Feng Yin, Sin-Yi Yang, Chen-Jung Wang, Yin-Hao Wu, Kun-Yi Li, Meng-Chieh Wen, Lin-Ting Lin, Jiann-Horng Lin, An-Shen Chang, Huan-Just Lin
  • Patent number: 11529083
    Abstract: A physiological status evaluation method and a physiological status evaluation apparatus are provided. The method includes the following: obtaining original electrocardiogram data of a user by an electrocardiogram detection apparatus; converting the original electrocardiogram data into digital integration data; obtaining a plurality of physiological characteristic parameters according to the digital integration data; filtering the physiological characteristic parameters for at least one notable characteristic parameter through at least one filter model, where decision importance of the at least one notable characteristic parameter in a decision process of the at least one filter model is greater than a threshold; building a prediction model according to the at least one notable characteristic parameter; and evaluating a physiological status of the user through the prediction model.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: December 20, 2022
    Assignees: Acer Incorporated, Taipei Veterans General Hospital, Acer Medical Inc.
    Inventors: Chun-Hsien Li, Tsung-Hsien Tsai, Jun-Hong Chen, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
  • Publication number: 20220079463
    Abstract: A physiological status evaluation method and a physiological status evaluation apparatus are provided. The method includes the following: obtaining original electrocardiogram data of a user by an electrocardiogram detection apparatus; converting the original electrocardiogram data into digital integration data; obtaining a plurality of physiological characteristic parameters according to the digital integration data; filtering the physiological characteristic parameters for at least one notable characteristic parameter through at least one filter model, where decision importance of the at least one notable characteristic parameter in a decision process of the at least one filter model is greater than a threshold; building a prediction model according to the at least one notable characteristic parameter; and evaluating a physiological status of the user through the prediction model.
    Type: Application
    Filed: October 29, 2020
    Publication date: March 17, 2022
    Applicants: Acer Incorporated, Taipei Veterans General Hospital, Acer Healthcare Inc.
    Inventors: Chun-Hsien Li, Tsung-Hsien Tsai, Jun-Hong Chen, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
  • Publication number: 20220084635
    Abstract: The disclosure provides a disease classification method and a disease classification device. The disease classification method includes: inputting samples into a first stage model and obtaining a first stage determination result; inputting first samples determined positive by the first stage model into a second stage high specificity model to obtain second samples determined to be positive and third samples determined to be negative and rule in the second samples; inputting fourth samples determined negative by the first stage model into a second stage high sensitivity model to obtain fifth samples determined to be positive and sixth samples determined to be negative and rule out the sixth samples; obtaining a second stage determination result of the second and sixth samples; and inputting the third and fifth samples not ruled in or ruled out into a third stage model and obtaining a third stage determination result of the third and fifth samples.
    Type: Application
    Filed: October 29, 2020
    Publication date: March 17, 2022
    Applicants: Acer Incorporated, Acer Healthcare Inc., Taipei Veterans General Hospital
    Inventors: Jun-Hong Chen, Tsung-Hsien Tsai, Chun-Hsien Li, Wei-Ting Wang, Yin-Hao Lee, Hao-Min Cheng
  • Publication number: 20220029091
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Hsiang WANG, Han-Ting LIN, Yu-Feng YIN, Sin-Yi YANG, Chen-Jung WANG, Yin-Hao WU, Kun-Yi LI, Meng-Chieh WEN, Lin-Ting LIN, Jiann-Horng LIN, An-Shen CHANG, Huan-Just LIN
  • Patent number: 11174157
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Yu-Hsuan Tsai, Yin-Hao Chen, Hsin Lin Wu, San-Kuei Yu
  • Patent number: 10750265
    Abstract: The present invention provides a smart speaker with fragrance dispenser. A housing is disposed below a lid. One or more air outlet, one or more air inlet, and one or more sound outlet are disposed on one side of the housing. A fragrance module is disposed on the inner side of the housing for outputting fragrance. A speaker and the fragrance module are disposed separately. A dot-matrix display is disposed on one side of the speaker. The speaker outputs sound and the dot-matrix display outputs light. A processor is disposed below the speaker and connected electrically to the fragrance module, the speaker, and the dot-matrix display for controlling the output of fragrance, sound, and light. The present invention further adopts a limiting member so that the lid can rotate and slide on the fragrance module.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Elitegroup Computer Systems Co., Ltd.
    Inventors: Fang-Yang Liao, Kai-Chuan Hsieh, Yin-Hao Chang
  • Publication number: 20200002162
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Yu-Hsuan TSAI, Yin-Hao CHEN, Hsin Lin WU, San-Kuei YU
  • Patent number: 9811628
    Abstract: Embodiments of the invention relate to a configurable register file for inclusion in ASIC and other integrated circuit designs such as those based on metal configurable standard cell (MCSC) technology. According to certain general aspects, configurable register files provided by the present embodiments improve area, power and routing efficiencies and flexibility over conventional approaches such as hard memory macros and RTL designs. In embodiments, a configurable register file is implemented as a soft macro constructed from metal configurable standard cell (MCSC) base cells. According to certain aspects, unlike a hard memory macro, width and depth are not fixed and can be configured or programmed to any desired dimension or configuration. In some embodiments, a bit array of a configurable register file is comprised of register file bit cells. In other embodiments, a bit array of a configurable register file is comprised of ROM bit cells.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: November 7, 2017
    Assignee: BaySand Inc.
    Inventors: Jonathan C. Park, Yau Kok Lai, Teck Siong Ong, Yin Hao Liew
  • Patent number: 9590634
    Abstract: Embodiments of the invention relate to a metal configurable hybrid memory for use in integrated circuit designs for implementation in structured ASIC or similar platforms utilizing a base cell or standard cell. In accordance with certain aspects, a hybrid memory according to embodiments of the invention utilizes a fixed custom memory core and a customizable peripheral set of base cells. In accordance with these and further aspects, the hybrid memory can be specified using a macro, in which certain memory features (e.g. ECC, etc.) are implemented using the customizable peripheral set of base cells, and which may be selected or omitted from the design by the user. This enables the overall logic use for the memory to be optimized for a user's particular design.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: March 7, 2017
    Assignee: BAYSAND INC.
    Inventors: Jonathan C. Park, Yau Kok Lai, Teck Siong Ong, Yin Hao Liew
  • Patent number: 9577640
    Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: February 21, 2017
    Assignee: Baysand Inc.
    Inventors: Jonathan C Park, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
  • Patent number: 9401717
    Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 26, 2016
    Assignee: Baysand Inc.
    Inventors: Jonathan C Parks, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
  • Publication number: 20160048482
    Abstract: A method for automatically partitioning an article into various chapters and sections is provided and applicable for a digital article. Firstly, style combinations of a plurality of paragraphs of the digital article are recognized. Then, one or more paragraph features of the paragraphs having different style combinations are calculated. The paragraph feature may be the uniform distribution of paragraphs, the font size, the average number of words, the average paragraph spacing, or the combinations thereof. Hence, in accordance with each of the paragraph features, the style combinations are ranked. Then, a weighted average value is calculated according to the ranking of each the style combinations corresponding to the corresponding paragraph feature. And, paragraphs with weighted average values ranked in the first place are selected to be a plurality of candidate partition paragraphs. Lastly, the digital article is divided into a plurality of partitions according to the candidate partition paragraphs.
    Type: Application
    Filed: June 3, 2015
    Publication date: February 18, 2016
    Inventor: Yin-Hao Tsui
  • Patent number: D967756
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 25, 2022
    Inventors: Jing Ma, Xiang Yin Hao, Ke Miao