Patents by Inventor Yin Kheng Au
Yin Kheng Au has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170062311Abstract: A packaged IC device has a power bar assembly with one or more power distribution bars, mounted on top of the IC die, which enables assembly using a lead frame that does not include any power distribution bars. External power supply voltages are brought to the IC die by (i) a corresponding first bond wire that connects a lead frame lead to a corresponding die-mounted power distribution bar and (ii) a corresponding second bond wire that connects the power distribution bar to a corresponding bond pad on the IC die. As such, different types of packaged IC devices having different numbers and/or configurations of power distribution bars can be assembled using a single, generic lead frame design having a die pad, tie bars, and leads, but no power distribution bars.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventors: Chee Seng Foong, Yin Kheng Au, Ly Hoon Khoo, Wen Shi Koh, Pei Fan Tong
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Patent number: 9257403Abstract: An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.Type: GrantFiled: November 26, 2013Date of Patent: February 9, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Tu-Anh N. Tran, John G. Arthur, Yin Kheng Au, Chu-Chung Lee, Chin Teck Siong, Meijiang Song, Jia Lin Yap, Matthew J. Zapico
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Publication number: 20150303169Abstract: A method for forming a semiconductor device includes forming a first ball bond on a first contact pad, in which the first ball bond has a first wire segment of a bonding wire extending from the ball bond; forming a mid-span ball in the first wire segment at a first distance from the ball bond; and after the forming the mid-span ball, attaching the mid-span ball to a second contact pad to form a second ball bond.Type: ApplicationFiled: April 17, 2014Publication date: October 22, 2015Inventors: Tu-Anh N. Tran, Yin Kheng Au, Burton J. Carpenter, Chu-Chung Lee
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Publication number: 20150206829Abstract: A packaged semiconductor device has a lead frame, a semiconductor die, and bond wires. The lead frame has a two-dimensional array of leads with a subset of interior leads located in the interior of the array that do not extend to the perimeter of the array. The bond wires are connected to the semiconductor die and respective ones of the leads of the array.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Inventors: Yin Kheng Au, Seoh Hian Teh, Jia Lin Yap, Pey Fang Hiew, Ly Hoon Khoo
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Publication number: 20150145148Abstract: An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.Type: ApplicationFiled: November 26, 2013Publication date: May 28, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Tu-Anh N. Tran, John G. Arthur, Yin Kheng Au, Chu-Chung Lee, Chin Teck Siong, Meijiang Song, Jia Lin Yap, Matthew J. Zapico
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Publication number: 20150097278Abstract: Assembling a surface mount semiconductor device includes providing a lead frame structure with peripheral leads and additional bottom face contacts integral with frame members. Outer portions of the bottom face contact members are interposed between inner portions of adjacent pairs of the peripheral leads. A package body is formed by encapsulating the lead frame structure in which the frame members are positioned outside a side edge surface. The peripheral leads and the bottom face contact members project between the side edge surface of the package body and the frame members. The frame members are cut and the peripheral leads and the bottom face contact members are separated and electrically isolated from each other.Type: ApplicationFiled: August 14, 2014Publication date: April 9, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Zhigang Bai, Yin Kheng Au, Lan Chu Tan, Jinzhong Yao
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Publication number: 20150075849Abstract: A semiconductor device includes a lead frame having a flag and leads surrounding the flag. The flag includes a first die attach area and an interposer area. An insulated layer with at least one conductive trace is formed on the interposer area.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Inventors: Jia Lin Yap, Yin Kheng Au
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Patent number: 8933547Abstract: A lead frame for a packaged semiconductor device has multiple, configurable power bars that can be selectively electrically connected, such as with bond wires, to each other and/or to other leads of the lead frame to customize the lead frame for different package designs. One or more of the configurable power bars may extend into one or more cut-out regions in a die paddle of the lead frame, which allows for short bond wires to be used to connect the power bars to die pads of a semiconductor die mounted on the die paddle.Type: GrantFiled: November 21, 2013Date of Patent: January 13, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jia Lin Yap, Yin Kheng Au, Ahmad Termizi Suhaimi, Seng Kiong Teng, Boon Yew Low, Navas Khan Oratti Kalandar
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Publication number: 20140374892Abstract: A lead frame for a semiconductor device has a die pad for supporting a semiconductor die and intermediate lead fingers extending from a periphery of the package towards the die pad, and each having a bonding end near the die pad. Outer lead fingers are located adjacent respective tie bars edges, each outer lead finger extending from the periphery of the package towards the die pad. Each outer lead finger has a transverse region coupling two spaced longitudinal regions. The two spaced longitudinal regions each have a bonding region near the die pad. A semiconductor die is attached to the die pad and bond wires electrically couple connection pads of the semiconductor die to the bonding regions of each outer lead finger. Only one of the bond wires is bonded to the bonding region of the second longitudinal region.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Yit Meng Lee, Yin Kheng Au, Quentin D. Gunn
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Publication number: 20140374467Abstract: A capillary bonding tool for wire bonding includes a first section, a second section and a bonding section. The first section has a first outer peripheral sidewall, an opposing first inner sidewall that extends generally parallel to the central longitudinal axis, and a first opening surrounded by the first inner sidewall. The second section has a second outer peripheral sidewall, an opposing second inner sidewall that extends at an angle with respect to the central longitudinal axis, and a second tapered opening surrounded by the second inner sidewall. The bonding section has a peripheral ridge extending axially outwardly from the second inner sidewall of the second section. The peripheral ridge has a third outer peripheral sidewall, a third inner tubular sidewall that extends generally parallel to the central longitudinal axis and radially outwardly of the first inner sidewall, and a third opening surrounded by the third inner tubular sidewall.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Jia Lin Yap, Yin Kheng Au, Lai Cheng Law
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Patent number: 8853840Abstract: A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.Type: GrantFiled: February 21, 2013Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Yin Kheng Au, Pey Fang Hiew, Jia Lin Yap
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Publication number: 20140263584Abstract: A method of making an electrical connection includes passing a bond wire through a wire bonding system having a wire polisher and a wire bonding tool. The wire polisher removes contamination from a first portion of the bond wire. A first bond is then formed by bonding the first portion of the bond wire to a first contact such that the bond wire and the first device are electrically connected. A second bond is then formed by bonding a second portion of the bond wire to a second contact such that the first contact and the second contact are electrically connected.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Inventors: Jia Lin Yap, Yin Kheng Au, Poh Leng Eu, Hung Yang Leong, Mohd Rusli Ibrahim, Navas Khan Oratti Kalandar, Mohd Faizal Zul-Kifli
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Publication number: 20140231978Abstract: A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Inventors: Yin Kheng Au, Pey Fang Hiew, Jia Lin Yap
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Publication number: 20140110461Abstract: A system for cleaning bond wire for use by a wire bonding machine includes a bond wire supply station, a bond wire cleaning bath station, a bond wire neutralizing station, a bond wire drying station, and a wire bonding machine. In operation, the bonding machine is supplied with bond wire stored at the supply station, which is firstly de-oxidized with a cleaning solution in the cleaning bath station. Next, the cleaning solution on the bond wire is neutralized with a neutralizing liquid in the neutralizing station. The bond wire is then dried in the drying station. The speed of the bond wire passing through the cleaning bath station, neutralizing station and drying station is controlled by the wire bonding machine.Type: ApplicationFiled: December 16, 2012Publication date: April 24, 2014Inventors: Mohd Rusli Ibrahim, Yin Kheng Au, Poh Leng Eu
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Patent number: 8450841Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.Type: GrantFiled: August 1, 2011Date of Patent: May 28, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Li Ting Celina Ong, Yin Kheng Au, Zi-Song Poh
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Publication number: 20130032932Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.Type: ApplicationFiled: August 1, 2011Publication date: February 7, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Li Ting Celina ONG, Yin Kheng Au, Zi-Song Poh
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Publication number: 20110204498Abstract: A lead frame for a semiconductor package has a flag to which a semiconductor die is mounted. Tie bars are coupled to the flag. There is a first set of leads and each first set lead in the first set of leads has a first set lead parallel length and a first set lead tapered length. The first set lead parallel length of each first set lead has a constant width and edges that are parallel to edges of all other first set lead parallel lengths. A free end region of the first set lead tapered length of each first set lead provides a first set lead bond target region. There is a second set of leads disposed between a first one of the tie bars and the first set of leads. Each second set lead, in the second set of leads, has a second set lead parallel length and a second set lead tapered length.Type: ApplicationFiled: February 24, 2010Publication date: August 25, 2011Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Yin Kheng Au, Mohd Rusli Ibrahim, Meng Kong Lye, Zi Song Poh, Seng Kiong Teng, Kesyakumar V.C. Muniandy