Abstract: The present application discloses a semiconductor structure. The semiconductor structure includes: a substrate, the substrate being provided with a conductive structure; a first lower electrode and a second lower electrode sequentially stacked, the first lower electrode being located between the second lower electrode and the substrate, and the first lower electrode being electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, the first dielectric layer covering a sidewall surface of the first lower electrode, and the first upper electrode being located on one side of the first dielectric layer away from the first lower electrode; and a second dielectric layer and a second upper electrode, the second dielectric layer covering an inner wall and a bottom surface of the second lower electrode, and the second upper electrode filling the recess of the second lower electrode.

Abstract: The present application relates to a capacitor device and a manufacturing method thereof, and a memory. forming a first capacitor structure on a substrate, includes: a first capacitor dielectric layer, a first upper electrode, a plurality of first lower electrodes arranged at intervals; the first capacitor dielectric layer at least covers sidewalls of the first lower electrodes, and the first upper electrode fills up gaps at an outer side of the first capacitor dielectric layer; forming a second capacitor structure on the first capacitor structure, the second capacitor structure includes a second capacitor dielectric layer, a second upper electrode, and a plurality of second lower electrodes arranged at intervals; the second lower electrodes are of a U-shaped structure, bottoms of the second lower electrodes are in contact with tops of the first lower electrodes, the second capacitor dielectric layer is at least located on surfaces of the second lower electrodes.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure includes: a substrate, the substrate being provided with a conductive structure; a first lower electrode and a second lower electrode sequentially stacked, the first lower electrode being located between the second lower electrode and the substrate, and the first lower electrode being electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, the first dielectric layer covering a sidewall surface of the first lower electrode, and the first upper electrode being located on one side of the first dielectric layer away from the first lower electrode; and a second dielectric layer and a second upper electrode, the second dielectric layer covering an inner wall and a bottom surface of the second lower electrode, and the second upper electrode filling the recess of the second lower electrode.

Abstract: Provided are a semiconductor structure and a method for preparing the same. The method for preparing a semiconductor structure includes: a substrate is provided; a stacked structure is formed on the substrate; a first capacitor having a first bottom electrode, a first dielectric layer and a first top electrode is formed in the stacked structure, in which the first bottom electrode is of a columnar structure; and a second capacitor having a second bottom electrode, a second dielectric layer and a second top electrode is formed on the first capacitor, in which the second bottom electrode is of a concave structure. The second dielectric layer is formed between the second bottom electrode and the second top electrode, and the second dielectric layer is further formed between the second bottom electrodes of adjacent second capacitors.

Abstract: A furnace temperature control method for thermal budget balance includes the steps of: placing a plurality of batches of wafers in the furnace; processing the wafers in the furnace via a heat deposition process; adjusting temperature in the furnace during the heat deposition process so that the temperature in the furnace has a temperature gradient; and controlling and inverting the temperature gradient so that the wafers in the furnace have the same thermal budget, whereby the electric parameters of the processed wafers tend to become uniform. Accordingly, considering the influence of the thermal budget, the present invention adjusts the temperature in the furnace and balances the thermal budget of the wafers in the furnace to avoid that the electric parameters of the processed wafers have extreme values, thereby improving the yield rate.