Abstract: This disclosure relates generally to a method, device, and system for congestion control in a wireless network. One method performed by a first network element is disclosed. The method may include determining, based on DL resource availability, that a DL burst arrival time of a DL burst for a wireless device needs to be adjusted; and transmitting a first message to a core network in the wireless communication system, the first message comprising a DL burst arrival time adjustment indication for the wireless device indicating that a DL burst arrival time of a DL burst for the wireless device needs to be adjusted.

Abstract: A method of dynamic cluster manager failover includes routing data traffic associated with managing a plurality of indexers in a cluster to a first cluster manager, wherein the first cluster manager is associated with an active role and is operable to manage the plurality of indexers in the cluster. The method also includes transmitting periodic heartbeat request messages from a second cluster manager of the cluster to the first cluster manager, wherein the second cluster manager is associated with a standby role. Further, the method includes detecting, at the second cluster manager, a loss of heartbeat response messages from the first cluster manager. Also, the method includes receiving information from a set of indexers regarding a status of the first cluster manager and in response to a determination that the status of the first cluster manager is offline, promoting the second cluster manager to switch over to the active role.

Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

Abstract: Provided are an information transmission method and apparatus, a communication node, and a storage medium. The information transmission method applied to a first communication node includes the followings: determining paging capability indication information, where the paging capability indication information indicates the paging capability of the first communication node in an inactive state, and transmitting the paging capability indication information to a third communication node. The paging mechanism in the inactive state is effectively determined by using the method.

Abstract: A memory access method comprises adding routing information to a memory page table, so that a memory management unit (MMU) queries, in a process of performing address translation on a virtual address (VA), the memory page table to obtain the routing information. After querying the memory page table and obtaining a physical address (PA), the MMU may directly route the PA based on the routing information, whereby a system address decoder (SAD) is not needed for further decoding the PA.

Abstract: A computer-implemented method of providing for dynamic cluster manager failover includes routing data traffic associated with managing network components in a cluster to an active cluster manager, where the active cluster manager manages a plurality of network components in the cluster. The method also includes transmitting periodic heartbeat request messages from a standby cluster manager to the active cluster manager. Further, the method includes detecting a loss of heartbeat response messages from the active cluster manager, where the heartbeat response messages are transmitted from the standby cluster manager to the active cluster manager in response to the periodic heartbeat request messages. The method also includes promoting the standby cluster manager to an active role and re-routing the data traffic associated with managing the network components to the currently active cluster manager.

Abstract: A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.

Abstract: The present invention belongs to the field of heat exchanger design and analysis, and discloses a multiscale analysis method, system, media and device for thermal-mechanical coupling performance of a heat exchanger, and the method comprises: performing zone division on the heat exchanger, and establishing channel unit cell models for respective zones; calculating equivalent mechanical parameters by constructing equations for equivalent stiffness coefficients and flexibility coefficients with respect to deformation energy, setting nodal displacement constraints or performing unit strain and stress loading; constructing an equivalent model, and calculating a macroscopic stress field, a strain field and a displacement field of the whole heat exchanger under temperature and pressure loads under operating conditions, calculating microscopic stress field of mesoscale channels at locations of weak strength zones of the heat exchanger.

Abstract: The disclosed systems, structures, and methods are directed to a computer system including a PCIe protection controller as a part of a PCIe root complex that includes at least one root port. Each root port is configured to optionally connect to at least one endpoint device, and each endpoint device is designated as a secure endpoint device or a nonsecure endpoint device. The PCIe protection controller is configured to control outbound traffic to protect secure endpoint devices from access from any nonsecure components of the computer system. The PCIe protection controller may be further configured to control inbound traffic to prevent access to secure memory by nonsecure endpoint devices. The PCIe protection controller may be dynamically configured at runtime to designate endpoint devices as either secure or nonsecure.

Abstract: The present disclosure relates to a heatsink structure, comprising: a base, and a plurality of fins which extend from the base, wherein the base comprises a recess in at least one space between two adjacent fins, and wherein at least one fin comprises a tip that is designed to match the shape of the recess, such that two of the heatsink structures can be joined with each other by interlocking at least one tip of one heatsink structure with at least one recess of the other heatsink structure and vice versa.

Abstract: A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.

Abstract: Examples described herein provide a method including determining a model location of a physical model by an augmented reality (AR) control application; operating the AR control application to display a holographic body overlaying the physical model via a display device, wherein the holographic body is aligned with the physical model such that a portion of the physical model representing an anatomical structure appears aligned with the holographic body in a predetermined anatomical position; maintaining alignment of the holographic body overlaying the physical model on the display device in real-time while a user interacts with the physical model using a physical medical instrument to simulate a predetermined procedure; and providing haptic feedback to the user during the predetermined procedure.

Abstract: Systems and memory devices are disclosed for fully homomorphic encryption (FHE). The system may include a processing unit including: a data memory for storing coefficients for a polynomial; a twiddle factor (TF) memory for storing TF values associated with the polynomial; a TF register connected to the TF memory; a plurality of first registers connected to the data memory; a plurality of first MUXs connected to the first registers; a plurality of second registers connected to the plurality of first MUXs; a plurality of Butterfly (BF) cores connected to the plurality of the second registers and the TF register; wherein each of the plurality of BF cores is configured to, responsive to a control signal, perform a Butterfly Transform (BFT) operation based on two coefficients from the data memory and a TF value from the TF memory.

Abstract: A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.

Abstract: A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.

Abstract: A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.

Abstract: The present invention provides a heat management arrangement for an electronic device, in particular for a handheld electronic device. The heat management arrangement comprises an active cooling means comprising a heat sink and at least one airflow channel configured for convective heat transport to an environment by an airflow. Furthermore, the heat management arrangement comprises a passive cooling means configured to be arranged between the heatsink and a surface of the electronic device and comprising a highly heat conductive substance. The passive cooling means is configured to contact the surface of the electronic device and to enhance heat conduction between the surface of the electronic device and the heat sink. In addition or alternatively, the passive cooling means is configured to enhance heat conduction between the surface of the electronic device and the airflow channel.

Abstract: A method and system for application security. The methods and systems of the present disclosure improve application security and may be used to secure a host application and operating system from malicious fast applications. A request to access resources of the computing device is received from an application adapter of a fast application operating within a host application on the computing device. In response to a determination that the request is associated with resources included in a permission list of the fast application, the unique user identifier (UID) of the application adapter to the UID of the host application is translated by the operating system, which determines whether to allow the request based on the UID of the host application. Otherwise, the operating system determines whether to allow the request based on the UID of the application adapter.

Abstract: Systems and memory devices are disclosed for fully homomorphic encryption (FHE). The system may include a processing unit including: a data memory for storing coefficients for a polynomial; a twiddle factor (TF) memory for storing TF values associated with the polynomial; a TF register connected to the TF memory; a plurality of first registers connected to the data memory; a plurality of first MUXs connected to the first registers; a plurality of second registers connected to the plurality of first MUXs; a plurality of Butterfly (BF) cores connected to the plurality of the second registers and the TF register; wherein each of the plurality of BF cores is configured to, responsive to a control signal, perform a Butterfly Transform (BFT) operation based on two coefficients from the data memory and a TF value from the TF memory.

Abstract: A method and system for application security. The methods and systems of the present disclosure improve application security and may be used to secure a host application and operating system from malicious fast applications. A request to access resources of the computing device is received from an application adapter of a fast application operating within a host application on the computing device. In response to a determination that the request is associated with resources included in a permission list of the fast application, the unique user identifier (UID) of the application adapter to the UID of the host application is translated by the operating system, which determines whether to allow the request based on the UID of the host application. Otherwise, the operating system determines whether to allow the request based on the UID of the application adapter.