Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.

Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.

Abstract: A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving a bit voltage and a second terminal coupled to a first node. The diode has an anode coupled to the first node and a cathode coupled to a second node. The second node receives a word voltage. The first transistor has a control electrode, a first electrode coupled to the first node, and a second electrode.

Abstract: A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving a bit voltage and a second terminal coupled to a first node. The diode has an anode coupled to the first node and a cathode coupled to a second node. The second node receives a word voltage. The first transistor has a control electrode, a first electrode coupled to the first node, and a second electrode.