Abstract: A high speed dual modulus prescaler aims to be used on a frequency synthesizer of wireless communication systems to divide frequency of input signals. The high speed dual modulus prescaler includes a first D flip-flop, a second D flip-flop and a main control transistor. The main control transistor switches connection of the first D flip-flop and second D flip-flop. The main control transistor provides an OR gate state and an AND gate state to form an OR gate circuit and an AND gate circuit in the prescaler. Thereby the number of transistors in the prescaler can be reduced to increase operation speed and lower power consumption.

Abstract: A double-triggered logic circuit is a composite circuitry consisting of a plurality of PMOS, NMOS, inverters and a signal line. It includes an AND logic circuit and a XNOR logic circuit to generate an adjustable pulse mode to solve the problem of threshold voltage loss.

Abstract: A double-triggered logic circuit is a composite circuitry consisting of a plurality of PMOS, NMOS, inverters and a signal line. It includes an AND logic circuit and a XNOR logic circuit to generate an adjustable pulse mode to solve the problem of threshold voltage loss.

Abstract: A method for encoding images according to object shapes is provided. The method enables reduced usage of storage space when an image encoding system encodes a received image frame. The method uses a bottom-up and sequential approach for encoding coefficients. The coefficients in each subband are numbered using a tree structure, wherein level N subband is designated as a root of the whole tree, level (N-1) subbands are designated as roots of subtrees, and level (N=1) subbands are designated as terminal nodes of subtrees. The terminal nodes for one of the subtrees are numbered first, and then this subtree is numbered in the bottom-up sequence. After that, the terminal nodes for another subtree are numbered, and this numbering sequence continues to number all the other subtrees until the root of the tree has been numbered, so as to allow a bottom-up encoding process for the coefficient to be performed.

Abstract: In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.

Abstract: In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.

Abstract: The present invention discloses a method for enhancing the driving capability of a digital to analog converter, wherein a voltage higher/lower than the intended output voltage is used to pre-charge/pre-discharge the capacitor of the output load; when the capacitor is charged/discharged to near the intended output voltage, the operation is switched back to the normal mode; and the pre-charge operation may adopt the fixed charge voltage-varying charge time mode or the fixed charge time-varying charge voltage mode.

Abstract: A method for encoding images according to object shapes is provided. The method enables reduced usage of storage space when an image encoding system encodes a received image frame. The method uses a bottom-up and sequential approach for encoding coefficients. The coefficients in each subband are numbered using a tree structure, wherein level N subband is designated as a root of the whole tree, level (N?1) subbands are designated as roots of subtrees, and level (N=1) subbands are designated as terminal nodes of subtrees. The terminal nodes for one of the subtrees are numbered first, and then this subtree is numbered in the bottom-up sequence. After that, the terminal nodes for another substree are numbered, and this numbering sequence continues to number all the other subtrees until the root of the tree has been numbered, so as to allow a bottom-up encoding process for the coefficient to be performed.