Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computing device can include host circuitry configured to provide a physical function and guest circuitry configured to provide a virtual function. The host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis instead of a time-to-time basis that uses fixed value request identifiers in time slices. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A processing system includes physical function circuitry to execute virtual functions and a processing unit configured to operate in a first mode that allows more than one virtual function to execute on the physical function circuitry and a second mode that constrains the physical function circuitry to executing a single virtual function. A first virtual function modifies a state of the processing unit in response to the processing unit being in the second mode. A host driver executing on the processing unit modifies an operating mode indicator to indicate that the processing unit is operating in the first mode or to indicate that the processing unit is operating in the second mode. Microcode executing on the processing unit accesses the operating mode indicator to determine whether the processing unit is operating in the first mode or the second mode.

Abstract: A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: A processing system selects a reset sequence based on a sideband connected configuration of a plurality of processing units. The processing system identifies whether the plurality of processing units is in the sideband connected configuration, so that the plurality of processing units works together on assigned operations. Based on the identification, the processing system selects and executes one of a plurality of available reset sequences. The processing system is thus able to tailor the executed reset sequence for the configuration of the plurality of processing units, thereby reducing the number of overall system resets and improving processing efficiency.

Abstract: A large-scale UAV mission planning method includes constructing an objective function and its constraints; initializing a mission sequence and inserting customers into the mission sequence with the smallest objective function value to obtain a plurality of initial mission sequences; iteratively performing the update operations on the plurality of initial mission sequences. Fast acquisition of optimal missions is achieved by the invention. This invention solves the existing problem of not being able to obtain the optimal mission due to the complex and time-consuming calculation method and the difficulty of convergence of the algorithm.

Abstract: A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.

Abstract: A parallel processor is configured to enforce job limits for virtual functions to facilitate an expected quality of service for each of the virtual functions assigned to a virtual machine executing at the processing unit. A scheduler schedules well-behaving virtual functions prior to badly-behaving virtual functions to prevent badly-behaving virtual functions from consuming a disproportionate share of hardware resources, thereby mitigating an impact of the badly-behaving virtual functions on the quality of service of the well-behaving virtual functions.

Abstract: A processing system aligns rendering timing of an application executing at a guest virtual function to world switch timing of a host virtual machine. The host virtual machine sets a world switch interval based on a number of virtual functions (VFs) that share the parallel processor and a target maximum frame rate. The processing system delays submission of jobs for a VF to the parallel processor by an offset with respect to the world switch timing to ensure that the application starts generating a job for the parallel processor before the VF gains a time slice so the job will be ready for the parallel processor when the VF gains the time slice.

Abstract: A host processing system assigns unequal time slices at a parallel processor to virtual functions based on profiles of applications executing at the virtual functions and an available budget of the parallel processor. The host processing system calculates a world switch cycle interval and assesses an available processing budget of the parallel processor. The available budget indicates the amount of graphics processing time the parallel processor has not yet allocated to virtual functions for each world switch cycle interval.

Abstract: In a computing device, a hardware device (e.g., a parallel accelerated processor or graphics processing unit) is coupled to a bus, such as a peripheral component interconnect express (PCIe) bus. The hardware device supports physical partitioning that allows physical resources of the hardware device to be separated into different partitions. Examples of such physical resources include engine resources (e.g., compute resources, direct memory access resources), memory resources (e.g., random access memory), and so forth. Each physical partition is mapped to a physical function that is exposed to a host on the computing device in a manner that is compliant with the bus protocol, allowing software to access the physical partition in a conventional manner based on the bus protocol.

Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

Abstract: An apparatus and method for efficiently executing multiple processes by reducing an amount of memory usage of the processes. In various implementations, a computing system includes a first processor and a second processor that support parallel data applications stored on a remote server that provides cloud computing services to multiple users. The first processor creates multiple processes, referred to as “instances” in parallel computing platforms, for a particular application as users request to execute the application. When the first processor detects a function call of the application within a particular instance, the first processor searches for shareable data objects to be used by the second processor when executing the first instance of the function call, and frees data storage allocated to data objects that are already shared by one or more instances. Therefore, an amount of memory allocated for the multiple instances of the application is reduced.

Abstract: Systems and methods are provided related to a scheduler to receive a job request from a virtual function associated with a tenant for execution by at least one processing unit. The scheduler validates the job request in accordance with one or more defined restrictions associated with the tenant and, responsive to successful validation, provides the job request for execution by the processing unit via one or more physical functions associated with the processing unit. In certain embodiments, multi-level enforcement of the defined restrictions are provided via user-mode and kernel-mode drivers associated with the virtual function that are also enabled to validate job requests based on the defined restrictions.

Abstract: The embodiments of the present disclosure provide an antibody or antigen-binding fragment against SARS-CoV-2 spike(S) protein, comprising: three complementarity determining regions (HCDRs) of a heavy chain variable region or one or more variants thereof, the heavy chain variable region set forth as SEQ ID NO. 30 or SEQ ID NO. 46, each of the one or more variants having at most two amino acid changes compared to the corresponding CDR; and three complementarity determining regions (LCDRs) of a light chain variable region or one or more variants thereof, the light chain variable region set forth as SEQ ID NO. 32 or SEQ ID NO. 48, each of the one or more variants having at most two amino acid changes compared to the corresponding CDR.

Abstract: Resource use orchestration for multiple application instances is described. In accordance with the described techniques, a time interval for accessing a resource is divided into multiple time slots. In one or more implementations, the resource is a graphics processing unit. Each of a plurality of containers associated with an application is assigned to one of the multiple time slots according to a disbursement algorithm. A respective signal offset is provided to each container based on an assigned time slot of the container. The provided signal offsets cause the plurality of containers to access the resource for the application in a predetermined order.

Abstract: A system and method for efficiently scheduling tasks to multiple endpoint devices are described. In various implementations, a computing system has a physical hardware topology that includes multiple endpoint devices and one or more general-purpose central processing units (CPUs). A virtualization layer is added between the hardware of the computing system and an operating system that creates a guest virtual machine (VM) with multiple endpoint devices. The guest VM utilizes a guest VM topology that is different from the physical hardware topology. The processor of an endpoint device that runs the guest VM accesses a table of latency information for one or more pairs of endpoints of the guest VM based on physical hardware topology, rather than based on the guest VM topology. The processor schedules tasks on paths between endpoint devices based on the table.