Patents by Inventor Yincai Liu
Yincai Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11057002Abstract: This disclosure describes techniques for selecting one of a plurality of modes in which to operate an amplifier. The techniques include configuring input routing circuitry, coupled to first and second inputs of the amplifier, based on the selected one of the plurality of modes; selectively applying a resistance to an output of the amplifier, using feedback routing circuitry, based on the selected one of the plurality of modes; and selectively applying one of a plurality of reference voltages, using reference voltage routing circuitry, coupled to the first and the second inputs of the amplifier, based on the selected one of the plurality of modes.Type: GrantFiled: June 18, 2019Date of Patent: July 6, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Li Wang, Hanqing Wang, Tony Yincai Liu, Shurong Gu
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Publication number: 20200403578Abstract: This disclosure describes techniques for selecting one of a plurality of modes in which to operate an amplifier. The techniques include configuring input routing circuitry, coupled to first and second inputs of the amplifier, based on the selected one of the plurality of modes; selectively applying a resistance to an output of the amplifier, using feedback routing circuitry, based on the selected one of the plurality of modes; and selectively applying one of a plurality of reference voltages, using reference voltage routing circuitry, coupled to the first and the second inputs of the amplifier, based on the selected one of the plurality of modes.Type: ApplicationFiled: June 18, 2019Publication date: December 24, 2020Inventors: Li Wang, Hanqing Wang, Tony Yincai Liu, Shurong Gu
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Publication number: 20200091923Abstract: The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Inventors: Junbiao Ding, Tony Yincai Liu, Dennis A. Dempsey, John Jude O'Donnell
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Patent number: 10574247Abstract: The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.Type: GrantFiled: September 14, 2018Date of Patent: February 25, 2020Assignee: Analog Devices Global Unlimited CompanyInventors: Junbiao Ding, Tony Yincai Liu, Dennis A. Dempsey, John Jude O'Donnell
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Patent number: 10425098Abstract: Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.Type: GrantFiled: April 6, 2018Date of Patent: September 24, 2019Assignee: Analog Devices GlobalInventors: Tony Yincai Liu, Dennis A. Dempsey
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Patent number: 10288674Abstract: A electrochemical or other sensor interface circuit architecture can deliver substantial DC offset bias to an electrochemical or other sensor separately or independently from delivering a time-varying AC excitation signal, which can then be provided with higher resolution, which, in turn, can allow better resolution of the measured response signal providing the impedance characteristic of sensor condition. For example, a differential time-varying AC excitation signal for the sensor condition characteristic can be delivered separately and independently from a differential stable (e.g., DC or other) bias signal, such as by using separate digital-to-analog converters (DACs), so that providing the more stable signal does not limit the resolution and accuracy of the time-varying signal, such as by using up the dynamic range of a single DAC.Type: GrantFiled: May 4, 2017Date of Patent: May 14, 2019Assignee: Analog Devices GlobalInventors: GuangYang Qu, Junbiao Ding, Tony Yincai Liu, Shurong Gu, Yimiao Zhao, Hanqing Wang, Leicheng Chen
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Publication number: 20180323798Abstract: Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.Type: ApplicationFiled: April 6, 2018Publication date: November 8, 2018Inventors: Tony Yincai Liu, Dennis A. Dempsey
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Publication number: 20180321302Abstract: A electrochemical or other sensor interface circuit architecture can deliver substantial DC offset bias to an electrochemical or other sensor separately or independently from delivering a time-varying AC excitation signal, which can then be provided with higher resolution, which, in turn, can allow better resolution of the measured response signal providing the impedance characteristic of sensor condition. For example, a differential time-varying AC excitation signal for the sensor condition characteristic can be delivered separately and independently from a differential stable (e.g., DC or other) bias signal, such as by using separate digital-to-analog converters (DACs), so that providing the more stable signal does not limit the resolution and accuracy of the time-varying signal, such as by using up the dynamic range of a single DAC.Type: ApplicationFiled: May 4, 2017Publication date: November 8, 2018Inventors: GuangYang Qu, Junbiao Ding, Tony Yincai Liu, Shurong Gu, Yimiao Zhao, Hanqing Wang, Leicheng Chen
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Patent number: 9941894Abstract: A multiple output, multiple impedance string digital-to-analog converter (DAC) circuit can provide a first output having a first resolution in response to a first digital input signal and a second output having a second resolution in response to a second digital input signal. A main impedance string and a secondary impedance string can be coupled using switching networks to provide a first DAC output. By coupling additional switches to the main impedance string and by sharing the main impedance string, a second DAC output can be realized.Type: GrantFiled: May 4, 2017Date of Patent: April 10, 2018Assignee: Analog Devices GlobalInventors: Shurong Gu, Dennis A. Dempsey, GuangYang Qu, Hanqing Wang, Tony Yincai Liu
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Patent number: 8390335Abstract: A signal buffer amplifier with high linearity is provided. A circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal. The circuit also includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal coupled to the first source terminal. The circuit further includes a first signal path coupled in between a signal input and the first gate terminal, a second signal path coupled in between the signal input and the second gate terminal, and a signal output coupled to the second source terminal. The first signal path includes a filter.Type: GrantFiled: June 18, 2010Date of Patent: March 5, 2013Assignee: FutureWei Technologies, Inc.Inventors: Gong Tom Lei, Yincai Liu, Minsheng Li, Jun Xiong
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Patent number: 8179194Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.Type: GrantFiled: April 30, 2010Date of Patent: May 15, 2012Assignee: FutureWei Technologies, Inc.Inventors: Minsheng Li, Gong Tom Lei, Song Liu, Jun Xiong, Yincai Liu, Feiqin Yang, Zu Xu Qin
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Publication number: 20100327944Abstract: A signal buffer amplifier with high linearity is provided. A circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal. The circuit also includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal coupled to the first source terminal. The circuit further includes a first signal path coupled in between a signal input and the first gate terminal, a second signal path coupled in between the signal input and the second gate terminal, and a signal output coupled to the second source terminal. The first signal path includes a filter.Type: ApplicationFiled: June 18, 2010Publication date: December 30, 2010Applicant: FutureWei Technologies, Inc.Inventors: Gong Tom Lei, Yincai Liu, Minsheng Li
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Publication number: 20100283535Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.Type: ApplicationFiled: April 30, 2010Publication date: November 11, 2010Applicant: FutureWei Technologies, Inc.Inventors: Minsheng Li, Gong Tom Lei, Song Liu, Jun Xiong, Yincai Liu, Feiqin Yang, ZuXu Qin