Abstract: A refresh control circuit includes a control circuit, a counter circuit, and an indication circuit. When a refresh management feature is disabled, the control circuit outputs an all-bank normal refresh request or a same-bank normal refresh request according to an address command signal if the indication circuit outputs an invalid indication signal, or the control circuit outputs an all-bank refresh management refresh request or a same-bank refresh management refresh request according to a received address command signal if an indication signal is valid. The counter circuit counts an accumulative quantity of same-bank refreshes, and performs resetting in response to a counting result reaching a set upper limit value or an all-bank refresh request. The indication circuit outputs the valid indication signal if the counting result is in a preset range, or outputs the invalid indication signal if the counting result is not in a preset range.

Abstract: A counter circuit includes an addition circuit including counting circuits corresponding to binary bits, a subtraction circuit and control circuits. Each counting circuit obtains a carry signal and this-time bit value according to addend signal and bit value currently output by the counting circuit, outputs the carry signal to next counting circuit, and latches the this-time bit value in response to first clock and outputs same to output terminal of the counting circuit in response to second clock. The subtraction circuit is connected to the counting circuits, obtains present subtraction counting result according to present addition counting result and subtrahend signal and outputs same in response to a first refresh instruction. Each control circuit corresponds to a counting circuit, outputs, in response to second refresh instruction, corresponding bit of the present subtraction counting result to the counting circuit to serve as the bit value output by the counting circuit.

Abstract: A memory is provided in this application, including multiple group regions, a command decoding circuit, and a control circuit. Each group region includes multiple bank groups, and each bank group corresponds to one bank group address. An active instruction is received by the command decoding circuit, and the active instruction is decoded to obtain an active command signal. The bank group address, a row address, and the active command signal are received by the control circuit, and the row address is sent to one of the group regions based on the active command signal and the bank group address.

Abstract: A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.

Abstract: A memory read-write circuit includes a sense amplifier and a control signal generation module. A power voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and a first power voltage controlled and supplied by the first control signal is greater than a second power voltage controlled and supplied by the second control signal. A control signal generation module is configured to control, in a normal read-write mode, a pulse duration for generating the first control signal to be a first duration, and control, in a refresh mode, the pulse duration for generating the first control signal to be a second duration, the second duration being less than the first duration.

Abstract: A counter circuit includes multiple stages of counting circuits corresponding to binary bits, each stage being configured to: obtain a carry signal and a this-time bit value according to an addend signal and a bit value currently output by the stage, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock and output same to an output terminal of the stage of counting circuit in response to a second clock. An output of the counter circuit is composed of bit values output by the multiple stages and is a binary representation of a counting result. An addend signal of a start-stage counting circuit is a high-level signal and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage. The first and second clocks are obtained based on division of a system clock.

Abstract: The present application relates to a chip test method and apparatus, a computer device, and a readable storage medium thereof. The chip test method includes: applying a test signal to a to-be-tested chip; and sending a data signal to the to-be-tested chip such that the to-be-tested chip enters a test mode based on the test signal and the data signal, and regulating a test voltage of the to-be-tested chip.

Abstract: The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit provided with an output terminal, and configured to generate, under the control of a first control signal and a clock signal, a first differential signal according to a signal to be compared and a first reference signal; a second sampling circuit provided with an output terminal connected to the output terminal of the first sampling circuit, and configured to generate, under the control of a second control signal and the clock signal, a second differential signal according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal.

Abstract: A protection circuit can be applied in a chip, and include: a first protection unit and a first element to be protected, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal, the first element to be protected includes a first P-type transistor, and a gate of the P-type transistor is configured to receive the first output signal. When the chip enters a burn-in test, the first output signal is a high-level signal.

Abstract: An address decoding circuit includes a decoding unit corresponding to a bank group and including first NAND gates, an address selection signal outputted by each first NAND gate controls a corresponding bank in the bank group corresponding to the decoding unit. The first NAND gate includes a first input end connected to an address signal of a bank corresponding to the first NAND gate and a second input end connected to an output end of a second NAND gate or a third NAND gate, the second NAND gate includes a first input end connected to an enable signal and a second input end connected to a control signal, and the third NAND gate includes a first input end connected to the enable signal and a second input end connected to an inverted signal of the control signal.

Abstract: A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

Abstract: A refresh circuit includes: a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh.

Abstract: A refresh address counting circuit, a refresh address counting method, and a refresh address read-write circuit are provided. The refresh address counting circuit includes: a self-oscillation clock generation circuit, configured to generate, in each of refresh cycles, a self-oscillation clock signal based on at least one array activation signal upon acquiring a refresh signal; a self-oscillation mask circuit, configured to generate a self-oscillation mask signal under a preset refresh command; and a refresh address counter, configured to counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and to output a self-oscillation refresh address.

Abstract: A data processing circuitry includes: a preprocessing circuit, configured to receive an initial data signal and generate a data signal to be processed and an auxiliary data signal according to the initial data signal; and a drive circuit, connected with the preprocessing circuit and configured to: adjust an initial calibration code according to a preset scenario, to obtain a target calibration code; adjust a value of a drive resistance of the drive circuit according to the target calibration code; and adjust a drive capability of the data signal to be processed according to the auxiliary data signal and the adjusted drive resistance, to generate a target data signal.

Abstract: A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.

Abstract: A refresh address generation circuit includes: a refresh control circuit configured to sequentially receive first refresh commands and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset value or output a second clock signal when the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1; an address generator coupled to refresh control circuit, pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a first to-be-refreshed address in response to the first clock signal during each first refresh operation, the first to-be-refreshed address includes the first address, and changing the first address in response to the second clock signal.

Abstract: A counter circuit includes multiple stages of counting circuits corresponding to binary bits, each stage being configured to: obtain a carry signal and a this-time bit value according to an addend signal and a bit value currently output by the stage, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock and output same to an output terminal of the stage of counting circuit in response to a second clock. An output of the counter circuit is composed of bit values output by the multiple stages and is a binary representation of a counting result. An addend signal of a start-stage counting circuit is a high-level signal and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage. The first and second clocks are obtained based on division of a system clock.

Abstract: A data transmission circuit, a data transmission method and an electronic device are provided. The data transmission circuit includes a data processing circuit and a data driving circuit. The data processing circuit is configured to receive a first data signal in a parallel state and convert the first data signal into a second data signal in a serial state. The data driving circuit includes a driving main circuit and a driving regulation circuit. The driving regulation circuit is configured to reduce, in response to the driving regulation circuit being in an enabled state, a voltage difference of the second data signal, to shorten a charging and discharging time and implement driving enhancement. The driving main circuit is configured to perform driving on an enhanced second data signal to obtain a target transmission signal.

Abstract: A counter circuit includes an addition circuit including counting circuits corresponding to binary bits, a subtraction circuit and control circuits. Each counting circuit obtains a carry signal and this-time bit value according to addend signal and bit value currently output by the counting circuit, outputs the carry signal to next counting circuit, and latches the this-time bit value in response to first clock and outputs same to output terminal of the counting circuit in response to second clock. The subtraction circuit is connected to the counting circuits, obtains present subtraction counting result according to present addition counting result and subtrahend signal and outputs same in response to a first refresh instruction. Each control circuit corresponds to a counting circuit, outputs, in response to second refresh instruction, corresponding bit of the present subtraction counting result to the counting circuit to serve as the bit value output by the counting circuit.

Abstract: The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.