Patents by Inventor Ying-Cheng Wu
Ying-Cheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128211Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.Type: ApplicationFiled: April 27, 2023Publication date: April 18, 2024Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
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Patent number: 11961892Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11955459Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.Type: GrantFiled: March 7, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11929417Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 30, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11418206Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.Type: GrantFiled: May 28, 2021Date of Patent: August 16, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Shih-Hsiung Huang, Ying-Cheng Wu, Chien-Ming Wu, Kai-Yin Liu
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Publication number: 20220069831Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.Type: ApplicationFiled: May 28, 2021Publication date: March 3, 2022Inventors: SHIH-HSIUNG HUANG, YING-CHENG WU, CHIEN-MING WU, KAI-YIN LIU
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Patent number: 10630308Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.Type: GrantFiled: April 15, 2019Date of Patent: April 21, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ying-Cheng Wu, Shih-Hsiung Huang
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Publication number: 20200028518Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.Type: ApplicationFiled: April 15, 2019Publication date: January 23, 2020Inventors: YING-CHENG WU, SHIH-HSIUNG HUANG
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Patent number: 10367517Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.Type: GrantFiled: July 3, 2018Date of Patent: July 30, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ying-Cheng Wu, Shih-Hsiung Huang
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Patent number: 10312925Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.Type: GrantFiled: August 20, 2018Date of Patent: June 4, 2019Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chih-Lung Chen, Ying-Cheng Wu, Shih-Hsiung Huang
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Publication number: 20190165800Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.Type: ApplicationFiled: August 20, 2018Publication date: May 30, 2019Inventors: CHIH-LUNG CHEN, YING-CHENG WU, SHIH-HSIUNG HUANG
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Publication number: 20190097645Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.Type: ApplicationFiled: July 3, 2018Publication date: March 28, 2019Inventors: Ying-Cheng Wu, Shih-Hsiung Huang
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Patent number: 8760559Abstract: A miniaturization image capturing module includes a substrate unit, an image capturing unit, a fixing glue unit, and a lens unit. The substrate unit includes a hollow substrate body, a plurality of top conductive pads, a plurality of bottom conductive pads, a plurality of embedded conductive traces. The hollow substrate body has at least one receiving space, and each embedded conductive trace is electrically connected between at least one of the top conductive pads and at least one of the bottom conductive pads. The image capturing unit includes at least one image capturing chip received in the receiving space and electrically connected to the substrate unit. The fixing glue unit includes a fixing glue disposed in the receiving space and fixed between the hollow substrate body and the image capturing chip. The lens unit is disposed on the top side of the hollow substrate body.Type: GrantFiled: August 2, 2011Date of Patent: June 24, 2014Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology CorporationInventors: Ti-Lun Liu, Ying-Cheng Wu
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Publication number: 20130026589Abstract: A miniaturization active sensing module includes a substrate unit, an active sensing unit, and an optical unit. The substrate unit includes a substrate body, a plurality of first bottom conductive pads disposed on the bottom side of the substrate body, and a plurality of first conductive tracks embedded in the substrate body. The substrate body has at least one first groove formed therein. The active sensing unit includes at least one active sensing chip embedded in the first groove. The active sensing chip has at least one active sensing area and a plurality of electric conduction pads disposed on the top side thereof, and each first conductive track has two ends electrically contacted by one electric conduction pad and one first bottom conductive pad, respectively. The optical unit includes at least one optical element, disposed on the substrate body, for protecting the active sensing area.Type: ApplicationFiled: September 23, 2011Publication date: January 31, 2013Applicants: LITE-ON TECHNOLOGY CORPORATION, SILITEK ELECTRONIC (GUANGZHOU) CO., LTD.Inventors: YING-CHENG WU, KANG-WEI LEE
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Publication number: 20120314126Abstract: A miniaturization image capturing module includes a substrate unit, an image capturing unit, a fixing glue unit, and a lens unit. The substrate unit includes a hollow substrate body, a plurality of top conductive pads, a plurality of bottom conductive pads, a plurality of embedded conductive traces. The hollow substrate body has at least one receiving space, and each embedded conductive trace is electrically connected between at least one of the top conductive pads and at least one of the bottom conductive pads. The image capturing unit includes at least one image capturing chip received in the receiving space and electrically connected to the substrate unit. The fixing glue unit includes a fixing glue disposed in the receiving space and fixed between the hollow substrate body and the image capturing chip. The lens unit is disposed on the top side of the hollow substrate body.Type: ApplicationFiled: August 2, 2011Publication date: December 13, 2012Applicants: LITE-ON TECHNOLOGY CORPORATION, SILITEK ELECTRONIC (GUANGZHOU)CO.,LTDInventors: TI-LUN LIU, YING-CHENG WU
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Patent number: 8085547Abstract: An electronic elements carrier includes a body, at least an electronic element and a filler. The body includes a substrate having a plate and a dam formed on the peripheral of plate, a conductive layer mounted on a surface of the dam, and at least a cavity defined by the plate and the dam of the substrate. The electronic element is disposed in the cavity of the body. The filler is received in the cavity of the substrate for encapsulating, sealing and protecting the electronic element.Type: GrantFiled: November 30, 2007Date of Patent: December 27, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Cheng Wu, Kun-Hsiao Liu
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Patent number: 8072489Abstract: A chip package (101) and a lens module (103) mounted on the chip package are provided. The chip package includes a substrate (20), a first chip (40), a second chip (70), and a cover (80). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires (50a). The second chip is mounted above the first chip and above the wires connected with the first chip and is electrically connected with the substrate via a second plurality of wires (50b). The cover is mounted above the second chip and the wires connected with the second chip.Type: GrantFiled: November 3, 2006Date of Patent: December 6, 2011Assignee: Altus Technology Inc.Inventors: Ying-Cheng Wu, Ying-Tang Su
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Patent number: 7929033Abstract: An image sensor package includes a first substrate, an image sensor chip, a processing chip and a plurality of passive elements. The first substrate has a supporting surface and a bottom surface opposite to the supporting surface. The image sensor chip is disposed on the supporting surface and electrically connected to the first substrate. The image sensor chip package further includes a second substrate. The processing chip and the passive elements are mounted on the second substrate and electrically connected to the second substrate. The bottom surface of the first substrate defines a cavity for receiving the second substrate, the processing chip and the passive elements therein.Type: GrantFiled: July 14, 2008Date of Patent: April 19, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Chi-Kuei Lee, Ying-Cheng Wu