Abstract: A receiver for wired communication, includes a DC (direct current) level shift circuit and an analog-to-digital converter circuit. The DC level shift circuit is configured to receive a first signal and generate a second signal, in which the DC level shift circuit comprises a capacitor, and the DC level shift circuit is further configured to transmit a first common-mode voltage in a first voltage domain to a first terminal of the capacitor and transmit a second common-mode voltage in a second voltage domain to a second terminal of the capacitor before the first signal is received, and when the DC level shift circuit receives the first signal, the DC level shift circuit stops transmitting the first common-mode voltage and the second common-mode voltage to the capacitor. The analog-to-digital converter circuit is configured to generate a digital signal according to the second signal.

Abstract: A compensation circuit is applied to a successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) that includes a comparator, and the comparator includes a first transistor and a second transistor. The first transistor and the second transistor receive an input signal during a sampling phase, and the comparator determines at least one bit of a digital output code during a comparison phase. The compensation circuit includes a voltage generator coupled to the comparator for providing a first voltage to a first bulk of the first transistor and a second bulk of the second transistor during the sampling phase and providing a second voltage to the first bulk of the first transistor and the second bulk of the second transistor during the comparison phase.

Abstract: A latch includes at least one first standard cell logic gate and at least one second standard cell logic gate. The first standard cell logic gate includes a first input terminal, a second input terminal, a third input terminal, and a first output terminal. The second standard cell logic gate includes a fourth input terminal, a fifth input terminal, a sixth input terminal, and a second output terminal. The first input terminal and the second input terminal receive a first input signal. The third input terminal receives a first output signal. The first output terminal outputs a second output signal. The fourth input terminal receives the second output signal. The fifth input terminal and the sixth input terminal receive a second input signal. The second output terminal outputs the first output signal.

Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.

Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.

Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.

Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.

Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.

Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.

Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

Abstract: A miniaturization image capturing module includes a substrate unit, an image capturing unit, a fixing glue unit, and a lens unit. The substrate unit includes a hollow substrate body, a plurality of top conductive pads, a plurality of bottom conductive pads, a plurality of embedded conductive traces. The hollow substrate body has at least one receiving space, and each embedded conductive trace is electrically connected between at least one of the top conductive pads and at least one of the bottom conductive pads. The image capturing unit includes at least one image capturing chip received in the receiving space and electrically connected to the substrate unit. The fixing glue unit includes a fixing glue disposed in the receiving space and fixed between the hollow substrate body and the image capturing chip. The lens unit is disposed on the top side of the hollow substrate body.

Abstract: A miniaturization active sensing module includes a substrate unit, an active sensing unit, and an optical unit. The substrate unit includes a substrate body, a plurality of first bottom conductive pads disposed on the bottom side of the substrate body, and a plurality of first conductive tracks embedded in the substrate body. The substrate body has at least one first groove formed therein. The active sensing unit includes at least one active sensing chip embedded in the first groove. The active sensing chip has at least one active sensing area and a plurality of electric conduction pads disposed on the top side thereof, and each first conductive track has two ends electrically contacted by one electric conduction pad and one first bottom conductive pad, respectively. The optical unit includes at least one optical element, disposed on the substrate body, for protecting the active sensing area.

Abstract: A miniaturization image capturing module includes a substrate unit, an image capturing unit, a fixing glue unit, and a lens unit. The substrate unit includes a hollow substrate body, a plurality of top conductive pads, a plurality of bottom conductive pads, a plurality of embedded conductive traces. The hollow substrate body has at least one receiving space, and each embedded conductive trace is electrically connected between at least one of the top conductive pads and at least one of the bottom conductive pads. The image capturing unit includes at least one image capturing chip received in the receiving space and electrically connected to the substrate unit. The fixing glue unit includes a fixing glue disposed in the receiving space and fixed between the hollow substrate body and the image capturing chip. The lens unit is disposed on the top side of the hollow substrate body.

Abstract: An electronic elements carrier includes a body, at least an electronic element and a filler. The body includes a substrate having a plate and a dam formed on the peripheral of plate, a conductive layer mounted on a surface of the dam, and at least a cavity defined by the plate and the dam of the substrate. The electronic element is disposed in the cavity of the body. The filler is received in the cavity of the substrate for encapsulating, sealing and protecting the electronic element.

Abstract: A chip package (101) and a lens module (103) mounted on the chip package are provided. The chip package includes a substrate (20), a first chip (40), a second chip (70), and a cover (80). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires (50a). The second chip is mounted above the first chip and above the wires connected with the first chip and is electrically connected with the substrate via a second plurality of wires (50b). The cover is mounted above the second chip and the wires connected with the second chip.

Abstract: An image sensor package includes a first substrate, an image sensor chip, a processing chip and a plurality of passive elements. The first substrate has a supporting surface and a bottom surface opposite to the supporting surface. The image sensor chip is disposed on the supporting surface and electrically connected to the first substrate. The image sensor chip package further includes a second substrate. The processing chip and the passive elements are mounted on the second substrate and electrically connected to the second substrate. The bottom surface of the first substrate defines a cavity for receiving the second substrate, the processing chip and the passive elements therein.

Abstract: An image sensor package includes an image sensor chip, a sidewall, an encapsulation glass, conductive material, and a plurality of solder balls. The image sensor chip comprises a photosensitive area, a non-photosensitive area surrounding the photosensitive area, and a plurality of bonding pads formed on the non-photosensitive area. The sidewall is located on the non-photosensitive are and defines a plurality of first through holes aligned with and corresponding to the bonding pads. The encapsulation glass is located on the sidewall. A plurality of solder balls are formed on the encapsulation glass aligned with the bonding pads, respectively. The encapsulation glass defines a plurality of second through holes each corresponding to a bonding pad and a corresponding solder ball. The image sensor package further comprises a conductive material through which the first and second through holes penetrate.

Abstract: An exemplary imaging module package includes a lens module and an imaging sensor module. The lens module includes a housing having a hollow top portion and a hollow bottom portion coaxially aligned with the hollow top portion. The imaging sensor module is received in the hollow bottom portion. The imaging sensor module includes an imaging sensor connected to the substrate and secured to the bottom portion, a substrate spaced from the bottom portion and defining at least one recess therein, and a plurality of passive components received in the at least one recess and wholly disposed below the imaging sensor.

Abstract: An exemplary image sensor package includes a base, an image sensor chip, a bonding layer, and an imaging lens. The image sensor chip is disposed on the base. The image sensor chip includes a photosensitive area. The bonding layer is disposed on at least one of the image sensor chip and the base. The bonding pads surround the photosensitive area. The imaging lens is adhered onto the bonding layer and hermetically seals the photosensitive area with the bonding layer. The imaging lens is configured for forming images on the photosensitive area. The present invention also relates to a method for manufacturing the image sensor package.