Patents by Inventor Ying-Chiao Wang

Ying-Chiao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170221834
    Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9679901
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of active areas, and an isolation structure. The substrate has a device region and a peripheral region surrounding the device region. The active areas are located in the substrate in the device region. When viewed from above, the edges of the ends of the active areas adjacent to the boundary of the device region are aligned with each other, and the width of the ends of the active areas adjacent to the boundary of the device region is greater than the width of the other portions of the active areas. The isolation structure is disposed in the substrate and surrounds the active areas and is located in the peripheral region.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 13, 2017
    Assignees: United Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Chien-Ting Ho, Le-Tien Jung, Shih-Fang Tzou, Chin-Lung Lin, Harn-Jiunn Wang
  • Patent number: 9659873
    Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Publication number: 20170133479
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first spacer around the gate structure, and a contact etch stop layer (CESL) adjacent to the first spacer; forming a cap layer on the gate structure, the first spacer, and the CESL; and removing part of the cap layer for forming a second spacer adjacent to the CESL.
    Type: Application
    Filed: December 3, 2015
    Publication date: May 11, 2017
    Inventors: Ying-Chiao Wang, Chao-Hung Lin, Ssu-I Fu, Jyh-Shyang Jenq, Li-Wei Feng, Yu-Hsiang Hung
  • Publication number: 20170062349
    Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.
    Type: Application
    Filed: August 26, 2015
    Publication date: March 2, 2017
    Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Publication number: 20170062615
    Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A first doped layer containing a first type of dopant is formed on the substrate only in the first area. A second doped layer containing a second type of dopant is formed on the substrate only in the second area. An annealing step is performed to drive the first type of dopant and the second type of dopant into the substrate.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 2, 2017
    Inventors: Ying-Chiao Wang, Ssu-I Fu, Jyh-Shyang Jenq, Hon-Huei Liu, Yu-Hsiang Hung
  • Patent number: 9339028
    Abstract: The present invention provides a method for inhibiting microorganisms or plant pests using exfoliated clay/surfactant complex. The weight ratio of the exfoliated clay to the surfactant can range from 99/1 to 1/99. Preferably, the exfoliated clay is an inorganic layered clay on a nano scale and the surfactant is cationic, nonionic, anionic or amphoteric.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 17, 2016
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiang-Jen Lin, Ying-Chiao Wang, Pei-Ru Li
  • Publication number: 20140158186
    Abstract: Disclosed are a counter electrode and a dye-sensitized solar cell. The dye-sensitized solar cell includes a photo electrode, the counter electrode and an electrolytic solution. The counter electrode is disposed correspondingly to the photo electrode. The counter electrode includes a conductive layer and a catalytic layer. The catalytic layer is formed on a surface of the conductive layer facing the photo electrode. The catalytic layer includes FeS2. The electrolytic solution is disposed between the photo electrode and the counter electrode. The present invention is capable of significantly decreasing manufacturing costs of the counter electrode and the dye-sensitized solar cell.
    Type: Application
    Filed: March 5, 2013
    Publication date: June 12, 2014
    Applicants: National Taiwan Normal University, National Taiwan University
    Inventors: Chun-wei CHEN, Chia-chun CHEN, Di-yan WANG, Ying-chiao WANG
  • Publication number: 20130296270
    Abstract: The present invention provides a method for inhibiting microorganisms or plant pests using exfoliated clay/surfactant complex. The weight ratio of the exfoliated clay to the surfactant can range from 99/1 to 1/99. Preferably, the exfoliated clay is an inorganic layered clay on a nano scale and the surfactant is cationic, nonionic, anionic or amphoteric.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventors: Jiang-Jen Lin, Ying-Chiao Wang, Pei-Ru Li
  • Publication number: 20110301369
    Abstract: The present invention provides an exfoliated clay/surfactant complex for inhibiting microorganisms, viruses or plant pests. The weight ratio of the exfoliated clay to the surfactant can range from 99/1 to 1/99. Preferably, the exfoliated clay is an inorganic layered clay on a nano scale and the surfactant is cationic, nonionic, anionic or amphoteric.
    Type: Application
    Filed: January 17, 2011
    Publication date: December 8, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiang-Jen Lin, Ying-Chiao Wang, Pei-Ru Li