Patents by Inventor Ying-Ching Shih

Ying-Ching Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250233119
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Application
    Filed: April 1, 2025
    Publication date: July 17, 2025
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 12347739
    Abstract: A package structure including a semiconductor die, a redistribution circuit structure, a backside dielectric layer, conductive terminals, an electronic device, and an underfill is provided. The semiconductor die laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes redistribution conductive layers and thermal enhancement structures electrically insulated from the redistribution conductive layers, and the thermal enhancement structures are thermally coupled to the semiconductor die. The backside dielectric layer is disposed on the redistribution circuit structure. The conductive terminals penetrate through the backside dielectric layer. The electronic device is disposed over the backside dielectric layer and electrically connected to the redistribution circuit structure through the conductive terminals.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Wen-Chih Chiou
  • Publication number: 20250210450
    Abstract: A package structure is provided. The package structure includes a substrate, a die bonded to the substrate, a lid disposed over the die and the substrate, and an interface structure sandwiched between the die and the lid and including a first thermal interface material disposed at corners of a top surface of the die, and a second thermal interface material disposed a rest of the top surface of the die. A Young's modulus of the first thermal interface material is smaller than a Young's modulus of the second thermal interface material.
    Type: Application
    Filed: March 13, 2024
    Publication date: June 26, 2025
    Inventors: Chun-Yen Lan, Yu-Hsun Wang, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Yu-Wei Lin
  • Publication number: 20250210541
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes a first ring structure over the wiring substrate and surrounding the chip structure, wherein a first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure.
    Type: Application
    Filed: May 23, 2024
    Publication date: June 26, 2025
    Inventors: Chun-Yen Lan, Yu-Hsun Wang, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20250201583
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Application
    Filed: March 3, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20250192100
    Abstract: An SoIC structure including a first semiconductor die, second semiconductor dies, dummy dies, and a gap filling layer is provided. The second semiconductor dies are disposed over and electrically connected to the first semiconductor die. The dummy dies are disposed over the first semiconductor die to laterally surround the second semiconductor dies. The gap filling layer is disposed on the first semiconductor die to laterally encapsulate the dummy dies and the second semiconductor dies.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih
  • Publication number: 20250183237
    Abstract: A package structure includes a lower package including a first semiconductor die including a backside metal film on a backside of the first semiconductor die, an upper package attached to the lower package and electrically coupled to the lower package, and a thermally conductive underfill layer between the lower package and the upper package and contacting the backside metal film.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 5, 2025
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Patent number: 12294002
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 12272568
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20250105086
    Abstract: Various embodiments include integrated circuit packages and methods of forming integrated circuit packages. In an embodiment, a device includes: a package substrate; an integrated circuit device attached to the package substrate; a stiffener ring around the integrated circuit device and attached to the package substrate; a lid attached to the stiffener ring; a channel connected to an area between the lid and the integrated circuit device, the channel extending along at least one side of the integrated circuit device in a top-down view; and a thermal interface material in the channel and in the area between the lid and the integrated circuit device.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Inventors: Chun-Yen Lan, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20250096062
    Abstract: A package structure includes a package substrate, an interposer module on the package substrate, a thermal interface material (TIM) layer on the interposer module, and a package lid on the TIM layer, including a package lid foot portion attached to the package substrate, a package lid plate portion connected to the package lid foot portion, and a plurality of fins extending from the package lid plate portion into the TIM layer over the interposer module.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20250079283
    Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The insulating encapsulant laterally surrounds the first semiconductor die and the second semiconductor die, wherein the insulating encapsulant includes a first portion sandwiched in between the first semiconductor die and the second semiconductor die, the first portion has a first recessed part adjacent to an edge of the first semiconductor die, and a second recessed part adjacent to an edge of the second semiconductor die. The redistribution layer is disposed on and electrically connected to the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chen Li, Sung-Chi Chang, Chin-Chuan Chang, Wei-Jhan Tsai, Hao-Wei Lin, Ying-Ching Shih
  • Patent number: 12230605
    Abstract: A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Chih-Wei Wu, Szu-Wei Lu
  • Publication number: 20250054900
    Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yen Lan, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Yu-Wei Lin
  • Publication number: 20250046753
    Abstract: A method of manufacturing a semiconductor device, the method includes bonding a first die and a second die to a first side of a wafer, wherein after bonding the first die and the second die to the first side of the wafer, a gap is disposed between the first die and the second die, wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap, depositing a third dielectric layer on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap, forming a molding material over the third dielectric layer to fill the gap, and performing a planarization process to expose top surfaces of the first die and the second die.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: Chih-Wei Wu, Ying-Ching Shih
  • Patent number: 12183681
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, a molding compound, a bridge structure, through insulator vias, an insulating encapsulant, conductive bumps, a redistribution layer and seed layers is provided. The molding compound encapsulates the first and second semiconductor die. The bridge structure is disposed on the molding compound and electrically connects the first semiconductor die with the second semiconductor die. The insulating encapsulant encapsulates the bridge structure and the through insulator vias. The conductive bumps are electrically connecting the first and second semiconductor dies to the bridge structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the bridge structure. The seed layers are respectively disposed in between the through insulator vias and the redistribution layer.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih
  • Publication number: 20240395772
    Abstract: A package structure including a wiring substrate, semiconductor dies, and a dielectric layer is provided. The wiring substrate includes die bonding regions and guiding patterns (auxiliary patterns, or dummy patterns) distributed between the die bonding regions. The semiconductor dies are disposed on the die bonding regions and electrically connected to the wiring substrate, wherein the guiding patterns are electrically insulated from the semiconductor dies. The dielectric layer is disposed the semiconductor dies and the wiring substrate, wherein the dielectric layer covers and is in contact with the guiding patterns.
    Type: Application
    Filed: May 28, 2023
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Ying-Ching Shih
  • Publication number: 20240387432
    Abstract: A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20240387197
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Patent number: 12148661
    Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee