Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.

Abstract: A tool organizing device includes a housing having two side walls, a rear wall, a bottom wall, a front opening, and a peripheral fence extended from an upper wall for forming a compartment in the peripheral fence for receiving tool members, and having a number of rails for slidably attaching drawers, and having a number of apertures formed in the side walls for hooking tool members, a tray is selectively and detachably attached to the bottom wall with four posts and includes a peripheral fence extended upwardly from a board for forming a compartment above the board and within the peripheral fence and for receiving tool members, a panel is selectively attached to the housing for hooking tool members.

Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.

Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.

Abstract: A clutch includes a hub having a hub flange formed at a first end. The clutch further includes a clutch tube having a central aperture formed therein, a clutch tube flange, and a friction surface that is substantially planar. The central aperture is configured to receive the shaft and is substantially perpendicular to the friction surface. The clutch further includes a clutch plate having a clutch surface that is substantially planar and is in contact with the friction surface. The clutch further includes a fastener configured to couple the clutch plate to the hub; and a spring device configured to push the hub flange and the clutch tube flange away from one another and push the friction surface to contact the clutch surface.

Abstract: A method and apparatus for replacing two separate photo detectors chips and two photo emitters by a single photo detector chip and a single photo emitter. This is achieved by using CombiDisks having a flexible shaft. The flexible section allows for the bending of the CombiDisks so that the encoder disks are next to each other and tangent to the same vertical plane. This allows for the placement of both the x and the y sensors in a single plane. This will in turn allow for the two photo detectors to be integrated in a single semiconductor chip, saving a separate photo detector chip, and its associated packaging. This additional savings is significant since the packaging itself contributes to approximately one half of the cost of such a detector.