Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: This disclosure provides a test kit for testing a device under test (DUT) including a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having a nest and an interposer substrate installed under the nest.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT. The DUT includes an antenna and radiates a RF signal. The test kit further includes a reflector having a lower surface. The RF signal emitted from the antenna of the DUT is reflected by the reflector and a reflected RF signal is received by the antenna of the DUT.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT. The DUT includes an antenna and radiates a RF signal. The test kit further includes a reflector having a lower surface. The RF signal emitted from the antenna of the DUT is reflected by the reflector and a reflected RF signal is received by the antenna of the DUT.

Abstract: A wireless test system includes a load board having an upper surface and a lower surface. The load board has a testing antenna disposed on the load board. A socket for receiving a device under test (DUT) having an antenna structure therein is disposed on the upper surface of the load board. The antenna structure is aligned with the testing antenna. The wireless test system further includes a handler for picking up and delivering the DUT to the socket. The handler has a clamp for holding and pressing the DUT. The clamp is grounded during testing and functions as a ground reflector that reflects and reverses radiation pattern of the DUT from an upward direction to a downward direction toward the testing antenna.

Abstract: A wireless test system includes a load board having an upper surface and a lower surface. The load board has a testing antenna disposed on the load board. A socket for receiving a device under test (DUT) having an antenna structure therein is disposed on the upper surface of the load board. The antenna structure is aligned with the testing antenna. The wireless test system further includes a handler for picking up and delivering the DUT to the socket. The handler has a clamp for holding and pressing the DUT. The clamp is grounded during testing and functions as a ground reflector that reflects and reverses radiation pattern of the DUT from an upward direction to a downward direction toward the testing antenna.

Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC.

Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC.

Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC.

Abstract: A bias circuit for a radio frequency power amplifier includes a bias transistor having a collector, an emitter, and a base, wherein the collector is connected to a DC voltage source, the emitter is connected to a radio frequency transistor, and the base is connected to a bias voltage source. An inductor is connected between the base of the radio frequency transistor and the emitter of the bias transistor, for blocking part of a radio frequency input signal coupled back to the bias transistor. A capacitor is connected between the base of the bias transistor and ground, for directly conducting the part of the radio frequency input signal coupled back to the bias transistor, into the ground, thereby preventing the bias transistor from being driven into a saturation state.

Abstract: A radio frequency (RF) power amplifier module integrated with a power control loop is formed on a print circuit board and packaged within a mold. In order to minimize a whole size of the RF power amplifier module, capacitors with a smaller size are employed to substitute for prior art ceramic directional couplers. In addition to the capacitors, RF power amplifiers, matching circuits, power detectors, and a power control specific application integrated circuit are all integrated on the print circuit board without individual packages. Furthermore, the RF power amplifiers and the power detectors are formed on a common semiconductor substrate. Therefore, the RF power amplifier module has advantages of a small size and minimum parasitic impedance.

Abstract: The invention discloses a method for detecting defectives in an integrated circuit. The integrated circuit is composed of a plurality of transistors in parallel on a wafer. The method includes the following two steps: applying a bias to the transistors, and extracting the infrared images of the transistors.

Abstract: A bias circuit for a radio frequency power amplifier includes a bias transistor having a collector, an emitter, and a base, wherein the collector is connected to a DC voltage source, the emitter is connected to a radio frequency transistor, and the base is connected to a bias voltage source. An inductor is connected between the base of the radio frequency transistor and the emitter of the bias transistor, for blocking part of a radio frequency input signal coupled back to the bias transistor. A capacitor is connected between the emitter of the bias transistor and ground or between the base of the bias transistor and ground, for directly conducting the part of the radio frequency input signal coupled back to the bias transistor, into the ground, thereby preventing the bias transistor from being driven into a saturation state.

Abstract: A radio frequency (RF) power amplifier module integrated with a power control loop is formed on a print circuit board and packaged within a mold. In order to minimize a whole size of the RF power amplifier module, capacitors with a smaller size are employed to substitute for prior art ceramic directional couplers. In addition to the capacitors, RF power amplifiers, matching circuits, power detectors, and a power control specific application integrated circuit are all integrated on the print circuit board without individual packages. Furthermore, the RF power amplifiers and the power detectors are formed on a common semiconductor substrate. Therefore, the RF power amplifier module has advantages of a small size and minimum parasitic impedance.