Patents by Inventor Ying Chou

Ying Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabrication method of semiconductor package
    Patent number: 9991197
    Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 5, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Cheng Chen, Chi-Ching Ho, Shao-Tzu Tang, Yu-Che Liu, Ying-Chou Tsai
  • Photomask and method for fabricating integrated circuit
    Patent number: 9983473
    Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Yi-Jie Chen, Feng-Yuan Chiu, Ying-Chou Cheng, Kuei-Liang Lu, Ya-Hui Chang, Ru-Gun Liu, Tsai-Sheng Gau
  • Package structure and method for fabricating the same
    Patent number: 9978673
    Abstract: A package structure is provided, including a carrier, an electronic component disposed on the carrier and having a sensing area, an encapsulant formed on the carrier and encapsulating the electronic component and the sensing area, and a conductive layer formed on the encapsulant with the sensing area of the electronic component free from being covered by the conductive layer. The encapsulant prevents a user's finger from being in direct contact with the sensing area so as to protect the sensing area from being damaged and hence ensure normal operation of the electronic component.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 22, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Chien-Hui Wang, Chung-Yan Huang, Ying-Chou Tsai
  • SECURING UNIT FOR SECURING ADAPTER TO WRENCH
    Publication number: 20180126521
    Abstract: A wrench includes a handle and a driving head and a ratchet ring with a receiving hole is received in the driving head. An adapter is detachably inserted into the receiving hole and has a neck, an engaging portion and a reception hole. The neck on first end of the engaging portion has a first groove. A second groove is defined in the second end of the engaging portion. Multiple holes are defined through the bottom of the second groove and communicate with the reception hole. 33 A clip is engaged with the second groove and partially protrudes beyond the holes and exposed in the reception. A securing unit is connected to the driving head to secure or release the adapter. The receiving hole is connected with larger bits or sockets, and the adapter is connected with smaller bits or sockets.
    Type: Application
    Filed: November 10, 2016
    Publication date: May 10, 2018
    Inventor: Chin-Ying Chou
  • CRISPR/CAS GLOBAL REGULATOR SCREENING PLATFORM
    Publication number: 20180119141
    Abstract: Provided herein are methods for identifying genetic networks and methods of treating neurodegenerative disorders associated with ?-synuclein dysfunction.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 3, 2018
    Applicant: Massachusetts Institute of Technology
    Inventors: Ying-Chou Chen, Fahim Farzadfard, Timothy Kuan-Ta Lu
  • Compositions and methods for making low thermal expansion ceramic bodies
    Patent number: 9932272
    Abstract: Comminuted pre-mixtures for technical ceramics production, and ceramic bodies made therefrom, the comminuted pre-mixtures being comprised of cellulosic components and alumina source components and the bodies being produced by compounding the comminuted pre-mixtures with powdered inorganic components into batch mixtures, adding liquids to the batch mixtures to form plastic batches, forming the plastic batches into shaped bodies, and heating the shaped bodies to form the ceramic bodies.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: April 3, 2018
    Assignee: Corning Incorporated
    Inventors: Kevin Ying Chou, Sumalee L. Likitvanichkul, Bryan Ray Wheaton
  • Method for Validating Measurement Data
    Publication number: 20180066939
    Abstract: A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using a detector in the measurement tool to obtain measurement data, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Inventors: Chui-Jung Chiu, Jen-Chieh Lo, Ying-Chou Cheng, Ru-Gun Liu
  • METHOD OF FABRICATING ELECTRONIC PACKAGE
    Publication number: 20180068896
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 8, 2018
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20180061747
    Abstract: A package structure is provided, including a carrier, an electronic component disposed on the carrier and having a sensing area, an encapsulant formed on the carrier and encapsulating the electronic component and the sensing area, and a conductive layer formed on the encapsulant with the sensing area of the electronic component free from being covered by the conductive layer. The encapsulant prevents a user's finger from being in direct contact with the sensing area so as to protect the sensing area from being damaged and hence ensure normal operation of the electronic component.
    Type: Application
    Filed: January 4, 2017
    Publication date: March 1, 2018
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Chien-Hui Wang, Chung-Yan Huang, Ying-Chou Tsai
  • Fabrication method of packaging substrate
    Patent number: 9899235
    Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Ying-Chou Tsai, Sheng-Che Huang
  • Method for validating measurement data
    Patent number: 9823066
    Abstract: A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature by using a source in the measurement tool having a tool setting parameter, collecting a response signal from the material feature by using a detector in the measurement tool to obtain measurement data, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature using the tool setting parameter. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chui-Jung Chiu, Jen-Chieh Lo, Ying-Chou Cheng, Ru-Gun Liu
  • Elliptical exerciser
    Patent number: 9814932
    Abstract: An elliptical exerciser includes a frame, first and second magnetic control wheel units, first and second swing levers, first and second transmission rods, first and second guiding mechanisms, first and second pedal rods, and a magnetic mechanism. When the first and second swing levers and the first and second transmission rods are swung forward and rearward synchronously and the first and second pedal rods are pedaled up and down to slide forward and rearward, the first and second pedal rods pivotally connected with bottom ends of the first and second swing levers are to do a tread motion of an elliptical trajectory.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: November 14, 2017
    Inventor: Ying-Chou Lai
  • Electronic package and fabrication method thereof
    Patent number: 9805979
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 31, 2017
    Assignee: Siliconware Precision Industires Co., Ltd.
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • FABRICATION METHOD OF SEMICONDUCTOR PACKAGE
    Publication number: 20170294372
    Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Chia-Cheng Chen, Chi-Ching Ho, Shao-Tzu Tang, Yu-Che Liu, Ying-Chou Tsai
  • FABRICATION METHOD OF CIRCUIT STRUCTURE
    Publication number: 20170273185
    Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Shao-Tzu Tang, Ying-Chou Tsai
  • Circuit structure and fabrication method thereof
    Patent number: 9699910
    Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: July 4, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-tzu Tang, Ying-Chou Tsai
  • RATCHET WRENCH
    Publication number: 20170182642
    Abstract: A ratchet wrench may comprise a main body, a circular ratchet gear, a locating unit, a spring and at least an accessory tool. The main body has an operating rod and a head portion, and an operating hole penetrates through a central portion of the head portion. Also, the ratchet gear is installed inside the operating hole. The locating unit is configured to extend toward an interior of the operating hole through an engaging portion thereof, and a peripheral groove is located at an end of the accessory tool along an outer periphery thereof. By engaging the engaging portion of the locating unit with the peripheral groove of the accessory tool, the accessory tool inserted into the connecting hole is configured to be secured on the main body for operation.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 29, 2017
    Applicant: POWAGRIP INDUSTRIAL CO., LTD.
    Inventor: Chin-Ying Chou
  • PHOTOMASK AND METHOD FOR FABRICATING INTEGRATED CIRCUIT
    Publication number: 20170160633
    Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.
    Type: Application
    Filed: February 17, 2017
    Publication date: June 8, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu LIN, Yi-Jie CHEN, Feng-Yuan CHIU, Ying-Chou CHENG, Kuei-Liang LU, Ya-Hui CHANG, Ru-Gun LIU, Tsai-Sheng GAU
  • Socket
    Patent number: D801769
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: November 7, 2017
    Assignee: Powagrip Industrial Co., Ltd.
    Inventor: Chin-Ying Chou
  • Smart home control device
    Patent number: D811392
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 27, 2018
    Assignees: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Wen Lu, Chih-Ling Lin, Yu-Ying Chou