Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: An exemplary notebook computer includes a smart battery, a number of status indicator lights, a function key and a control unit electrically coupled to the smart battery, the status indicator lights and the function key. In the condition that the notebook computer is situated either in a shutdown mode or in a power saving mode and the function key is pressed, the control unit reads the data of the remaining capacity of the smart battery through a bus between the smart battery and the control unit so as to calculate the remaining capacity of the smart battery. Thus, the control unit can control the status indicator lights to be light on/off to display the information of the remaining capacity of the smart battery.

Abstract: An exemplary notebook computer includes a smart battery, a number of status indicator lights, a function key and a control unit electrically coupled to the smart battery, the status indicator lights and the function key. In the condition that the notebook computer is situated either in a shutdown mode or in a power saving mode and the function key is pressed, the control unit reads the data of the remaining capacity of the smart battery through a bus between the smart battery and the control unit so as to calculate the remaining capacity of the smart battery. Thus, the control unit can control the status indicator lights to be light on/off to display the information of the remaining capacity of the smart battery.

Abstract: A computer system comprises a chip set having a PCI Express controller with a preset lane width, a PCI Express connector with a relative bigger lane width, and a PCI Express interfaced apparatus with the bigger lane width. In the system, only part of the contacts within the PCI Express connector is connected to the PCI Express controller while the other contacts are opened.

Abstract: A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects to the PCI Express connector. The PCI Express connector has a trench formed at an edge thereof. The PCI Express daughter board has a connecting portion with a number of golden fingers greater than a number of contacts of the PCI connector. The PCI Express connector is capable to pair the daughter board with part of the golden fingers located outside the connector.

Abstract: Methods for switching system modules in a computer system. The computer system includes a first system module, a second system module, and system programs. The system programs include a first and a second system program, corresponding to the first and second system modules respectively. A switching component, such as a transistor, is first provided. An address control signal from the switching component is then received. The first system program is executed if the address control signal is a first signal. Otherwise, the second system program is executed if the address control signal is a second signal.

Abstract: A module with a first Northbridge area comprising a first CPU, a first system memory, a first accelerated graphics port and a first Northbridge is provided. A motherboard with a Southbridge and a second Northbridge area comprising a second CPU, a second system memory, a second accelerated graphics port and a second Northbridge is also provided. A bus switching device and an expansion connector for connection of the module is provided on the motherboard. When the module is not connected the expansion connector, the second Northbridge area is connected with the Southbridge and the expansion connector is disconnected from the Southbridge; and when the module is connected the expansion connector, the second Northbridge area is disconnected from the Southbridge, and the Southbridge is electrically connects with the expansion connector.

Abstract: A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects to the PCI Express connector. The PCI Express connector has a trench formed at an edge thereof. The PCI Express daughter board has a connecting portion with a number of golden fingers greater than a number of contacts of the PCI connector. The PCI Express connector is capable to pair the daughter board with part of the golden fingers located outside the connector.

Abstract: A computer system comprises a chip set having a PCI Express controller with a preset lane width, a PCI Express connector with a relative bigger lane width, and a PCI Express interfaced apparatus with the bigger lane width. In the system, only part of the contacts within the PCI Express connector is connected to the PCI Express controller while the other contacts are opened.

Abstract: A system having a mother board with a PCI controller and an AGP connector formed thereon is provided. Part of the electric contacts within the AGP connector is connected to the PCI controller and the rest contacts are opened.

Abstract: A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects to the PCI Express connector. The PCI Express connector has a trench formed at an edge thereof. The PCI Express daughter board has a connecting portion with a number of golden fingers greater than a number of contacts of the PCI connector. The PCI Express connector is capable to pair the daughter board with part of the golden fingers located outside the connector.