Abstract: A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.

Abstract: A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.

Abstract: An amplifier circuit and an operation method thereof are provided. The amplifier circuit includes two stages of amplifiers. When the amplifier circuit is operated in a high gain mode, the two stages of amplifiers are operated normally to provide high gain. When the amplifier circuit is operated in a low gain mode, the second stage of amplifier is turned off, and the first stage of amplifier is coupled to output terminals of the amplifier circuit through signal isolation elements so as to form a single stage of amplifier. Therefore, the amplifier circuit can change the total gain value thereof according to a requirement of gain.

Abstract: An amplifier circuit and an operation method thereof are provided. The amplifier circuit includes two stages of amplifiers. When the amplifier circuit is operated in a high gain mode, the two stages of amplifiers are operated normally to provide high gain. When the amplifier circuit is operated in a low gain mode, the second stage of amplifier is turned off, and the first stage of amplifier is coupled to output terminals of the amplifier circuit through signal isolation elements so as to form a single stage of amplifier. Therefore, the amplifier circuit can change the total gain value thereof according to a requirement of gain.

Abstract: A variable gain amplifier circuit is disclosed. The variable gain amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first gain switching circuit, and a second gain switching circuit. The first and the second transistors are respectively coupled to the first and the second nodes for receiving a differential input signal pair. The third transistor is coupled between the first node and a third node. The fourth transistor is coupled between the second node and a fourth node. The first gain switching circuit is coupled between the first node and the third node and further cross-coupled to the fourth node. The second gain switching circuit is coupled between the second node and the fourth node and further cross-coupled to the third node.

Abstract: A fast bias circuit including a bias unit, a resistor, a first switch, and a detecting circuit is provided. The resistor has a first terminal coupled to the bias unit to receive a bias voltage, and a second terminal coupled to a bias terminal of a target circuit, wherein the bias terminal is coupled to an input signal. The first switch has a first terminal coupled to the first terminal of the resistor, a second terminal coupled to the second terminal of the resistor, and a control terminal coupled to the detecting circuit. During an initialisation period, the detecting circuit compares the bias voltage with a voltage at the bias terminal of the target circuit to obtain a comparison result, and controls the first switch according to the comparison result. Furthermore, a fast bias method and a bias and load circuit are also provided.

Abstract: A variable gain amplifier circuit is disclosed. The variable gain amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first gain switching circuit, and a second gain switching circuit. The first and the second transistors are respectively coupled to the first and the second nodes for receiving a differential input signal pair. The third transistor is coupled between the first node and a third node. The fourth transistor is coupled between the second node and a fourth node. The first gain switching circuit is coupled between the first node and the third node and further cross-coupled to the fourth node. The second gain switching circuit is coupled between the second node and the fourth node and further cross-coupled to the third node.

Abstract: An automatic gain control device includes a variable-gain amplifier, a power detector, a gain control unit and a frequency response unit. The variable-gain amplifier is implemented for determining a gain according to a gain control signal and generating an amplified signal by amplifying a received signal according to the gain. The power detector is implemented for determining a power of a frequency response result and accordingly outputting a detection result. The gain control unit is implemented for outputting the gain control signal according to the detection result. The frequency response unit is implemented for performing a frequency response operation on the amplified signal to generate the frequency response result.

Abstract: An amplifier with wide gain range includes a signal converting unit, a channel unit, and multiple amplifiers. The signal converting unit receives a gain modulation signal and accordingly outputs multiple modulation signals and multiple selection signals. Based on a level of the gain modulation signal, one of the selection signals is set at a first logic state and the other selection signals are at a second logic state. The channel unit has multiple channels, respectively controlled by the selection signals, so as to conduct the channel with at the first logic state. The amplifiers are connected in series. Output terminals of the amplifiers are also respectively output to the channels of the channel unit. The amplifiers are also controlled by the modulation signals of the signal converting unit.

Abstract: An amplifier with wide gain range includes a signal converting unit, a channel unit, and multiple amplifiers. The signal converting unit receives a gain modulation signal and accordingly outputs multiple modulation signals and multiple selection signals. Based on a level of the gain modulation signal, one of the selection signals is set at a first logic state and the other selection signals are at a second logic state. The channel unit has multiple channels, respectively controlled by the selection signals, so as to conduct the channel with at the first logic state. The amplifiers are connected in series. Output terminals of the amplifiers are also respectively output to the channels of the channel unit. The amplifiers are also controlled by the modulation signals of the signal converting unit.

Abstract: An active balun circuit is provided, which includes an input end, a first and a second output ends, a first and a second transistors, a feedback capacitor, and a current source. The input end receives an input signal. A drain of the first transistor is coupled to the second output end, and a gate of the first transistor is coupled to the input end. A gate of the second transistor is coupled to a ground end, and a drain of the second transistor is coupled to the first output end. The feedback capacitor is coupled between the second output end and the gate of the second transistor. One end of the current source is coupled to sources of the first and second transistors, and the other end of the current source is coupled to the ground end.

Abstract: An active balun circuit is provided, which includes an input end, a first and a second output ends, a first and a second transistors, a feedback capacitor, and a current source. The input end receives an input signal. A drain of the first transistor is coupled to the second output end, and a gate of the first transistor is coupled to the input end. A gate of the second transistor is coupled to a ground end, and a drain of the second transistor is coupled to the first output end. The feedback capacitor is coupled between the second output end and the gate of the second transistor. One end of the current source is coupled to sources of the first and second transistors, and the other end of the current source is coupled to the ground end.