Patents by Inventor Ying Feng Wu

Ying Feng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101784
    Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng
  • Publication number: 20240096848
    Abstract: A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Wei Wu, Ching-Feng Yang, Ying-Ching Shih, An-Jhih Su, Wen-Chih Chiou
  • Patent number: 7592857
    Abstract: A charge-pump circuit without reverse current is disclosed. The charge-pump circuit includes: several diode equivalent networks connecting in series, between any two of adjacent diode equivalent networks having a node with a corresponding voltage-boost level, wherein the low voltage end in the diode equivalent network with lowest voltage-boost level is the input of the charge-pump circuit, and the input receives an input voltage signal; a voltage-boost capacitor network having an end to electronically couple to one of the node and the other end to electronically couple to a pulse signal, wherein the pulse signal has a high-voltage level and a low-voltage level to raise a voltage level at the node with voltage-boost as high-voltage level and low-voltage level switches; and a reverse current cut-off circuit electronically coupled to the diode equivalent networks to enable and disable the diode equivalent networks, wherein the reverse current cut-off circuit has two conductive paths.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: September 22, 2009
    Assignee: G-Time Electronic Co., Ltd.
    Inventors: Che-Ming Wu, Ying-Feng Wu
  • Patent number: 7589569
    Abstract: A comparator with a fixed reference voltage (self bias) for an oscillator is disclosed. The comparator includes: a depletion MOS network to form a source current, wherein the gate and the source has a connection; and an enhanced MOS transistor, wherein the drain or the source connects with the depletion MOS transistor in series. The gate of the enhanced MOS transistor receives an input voltage when the input voltage is lower than the reference voltage, and the comparator outputs a high level voltage, or the enhanced MOS transistor outputs a low level voltage if the input voltage is higher then the reference voltage. Moreover, the oscillator's comparator has a reference voltage that is independent from temperature and supply voltage source.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: September 15, 2009
    Assignee: G-Time Electronic Co., Ltd.
    Inventors: Ying-Feng Wu, Che-Ming Wu
  • Publication number: 20090058607
    Abstract: This invention discloses a RFID positioning apparatus and a method for identifying and positioning at least one RFID tag. The apparatus comprises a transmission module for transmitting a frequency, a capacitor, sensing modules, an identification module and circuit modules. A first switching unit of the sensing module performs a connection operation according to the frequency to form a magnetic flux of a induction coil and the capacitor, such that the first induction coil senses an identification signal of a RFID tag. The identification module receives the identification signal for identifying and positioning the RFID tag. Each circuit module is connected to the transmission module, sensing module, capacitor and identification module, and transmits the identification signal. The circuit modules have substantially equal length to achieve a matched status of all induction coils.
    Type: Application
    Filed: September 1, 2008
    Publication date: March 5, 2009
    Applicant: G-TIME ELECTRONIC CO., LTD.
    Inventors: TIEN-FA HOU, CHE-MING WU, YING-FENG WU
  • Publication number: 20080100389
    Abstract: A comparator with a fixed reference voltage (self bias) for an oscillator is disclosed. The comparator includes: a depletion MOS network to form a source current, wherein the gate and the source has a connection; and an enhanced MOS transistor, wherein the drain or the source connects with the depletion MOS transistor in series. The gate of the enhanced MOS transistor receives an input voltage when the input voltage is lower than the reference voltage, and the comparator outputs a high level voltage, or the enhanced MOS transistor outputs a low level voltage if the input voltage is higher then the reference voltage. Moreover, the oscillator's comparator has a reference voltage that is independent from temperature and supply voltage source.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 1, 2008
    Inventors: Ying-Feng Wu, Che-Ming Wu
  • Patent number: 7191953
    Abstract: The present invention discloses a radio frequency identification device implemented with a metal-gate semiconductor fabrication process, wherein the charge capacitor, which is formed by the special parasitic N-type and P-type guard rings in the chip fabricated with the metal-gate process, incorporated with the original P-type and N-type transistors of metal oxide semiconductor (PMOS/NMOS) not only can provide a horizontal surface current but also can provide a rectified current for the performance of the entire circuit, which can advance the metal gate process to RFID industry in cooperation with an identification code holder circuit and a non-synchronous local oscillation circuit so that the fabrication cost can be lowered and the fabrication time can be shortened.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: March 20, 2007
    Assignee: G-Time Electronic Co., Ltd.
    Inventors: Che Ming Wu, Ying Feng Wu, Wen Feng Lee