Patents by Inventor Ying-Han CHIOU
Ying-Han CHIOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047562Abstract: A method includes forming a semiconductor fin upwardly extending from a substrate; forming a gate strip extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and at opposite sides of the gate strip; forming a gate spacer on a sidewall of the gate strip; forming a film layer on the gate spacer; performing an etching process on the gate strip to break the gate strip into a first gate structure and a second gate structure, the etching process further consuming the gate spacer while remains the film layer; forming an isolation structure interposing the first and second gate structures.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Huan HSIN, Ying-Han CHIOU
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Patent number: 9818704Abstract: A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively.Type: GrantFiled: October 31, 2016Date of Patent: November 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Yao Wang, Ying-Han Chiou, Ling-Sung Wang
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Publication number: 20170047297Abstract: A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively.Type: ApplicationFiled: October 31, 2016Publication date: February 16, 2017Inventors: Yung-Yao Wang, Ying-Han Chiou, Ling-Sung Wang
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Patent number: 9484303Abstract: An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of low-k dielectric layers, and a metal line in the first dielectric layer. A stress tuning dielectric layer is over the first dielectric layer, wherein the stress tuning dielectric layer includes a first opening and a second opening. The metal line extends into the first opening. The second opening has a bottom substantially level with a top surface of the first dielectric layer. A second dielectric layer is over the first dielectric layer.Type: GrantFiled: July 19, 2013Date of Patent: November 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Yao Wang, Ying-Han Chiou, Ling-Sung Wang
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Patent number: 9337126Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.Type: GrantFiled: November 27, 2013Date of Patent: May 10, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hao Li, Ying-Han Chiou, Chi-Yen Lin
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Patent number: 9076751Abstract: Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure. The active electrical structure may include a capacitor, a resistor, a conductive line, a segment of a conductive line, a transistor, or a combination thereof.Type: GrantFiled: August 30, 2011Date of Patent: July 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia Yang Ko, Ying-Han Chiou, Ling-Sung Wang
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Publication number: 20150145119Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: Taiwan Semiconductor Manufacturing CO., LTD.Inventors: Chen-Hao Li, Ying-Han Chiou, Chi-Yen Lin
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Publication number: 20140264931Abstract: An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of low-k dielectric layers, and a metal line in the first dielectric layer. A stress tuning dielectric layer is over the first dielectric layer, wherein the stress tuning dielectric layer includes a first opening and a second opening. The metal line extends into the first opening. The second opening has a bottom substantially level with a top surface of the first dielectric layer. A second dielectric layer is over the first dielectric layer.Type: ApplicationFiled: July 19, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Yao Wang, Ying-Han Chiou, Ling-Sung Wang
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Patent number: 8659089Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.Type: GrantFiled: October 6, 2011Date of Patent: February 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Yang Ko, Ching-Chien Huang, Ying-Han Chiou, Ling-Sung Wang
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Publication number: 20130087857Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Yang Ko, Ching-Chien Huang, Ying-Han Chiou, Ling-Sung Wang
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Publication number: 20130049781Abstract: Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia Yang Ko, Ying-Han Chiou, Ling-Sung Wang
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Publication number: 20120313186Abstract: A polysilicon gate structure includes a substrate, a silicon dioxide layer disposed over the substrate, a nitrogen-doped high-k dielectric layer disposed over the silicon dioxide layer, and a polysilicon gate disposed over the nitrogen-doped high-k dielectric layer.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Chien HUANG, Ying-Han CHIOU, Ling-Sung WANG