Patents by Inventor Ying Hao Hsieh
Ying Hao Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071847Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
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Publication number: 20230387304Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying-Hao HSIEH
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Patent number: 11824120Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: GrantFiled: August 27, 2021Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying-Hao Hsieh
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Publication number: 20210391465Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying-Hao HSIEH
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Patent number: 11107921Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: GrantFiled: November 26, 2019Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
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Patent number: 10784375Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: GrantFiled: July 9, 2018Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
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Publication number: 20200098919Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying Hao HSIEH
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Patent number: 10446665Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.Type: GrantFiled: February 26, 2018Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Xiuyu Cai, Ying Hao Hsieh
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Publication number: 20180315855Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying Hao HSIEH
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Patent number: 10020397Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.Type: GrantFiled: June 5, 2015Date of Patent: July 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
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Publication number: 20180190787Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.Type: ApplicationFiled: February 26, 2018Publication date: July 5, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Xiuyu Cai, Ying Hao Hsieh
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Patent number: 9941388Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.Type: GrantFiled: June 19, 2014Date of Patent: April 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Xiuyu Cai, Ying Hao Hsieh
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Publication number: 20150372108Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.Type: ApplicationFiled: June 19, 2014Publication date: December 24, 2015Inventors: Xiuyu Cai, Ying Hao Hsieh
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Patent number: 9054130Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas.Type: GrantFiled: July 22, 2010Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eric Peng, Chao-Cheng Chen, Ming-Hua Yu, Ying Hao Hsieh, Tze-Liang Lee, Chii-Horng Li, Syun-Ming Jang, Shih-Hao Lo
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Publication number: 20130175585Abstract: Disclosed herein are various methods of forming faceted stress-inducing stressors proximate the gate structure of a transistor. In one example, a method includes forming a first recess in an active region of a semiconducting substrate, forming a first semiconductor material in the first recess and forming a gate structure above the first semiconductor material. In this example, the method includes the additional steps of performing a crystalline orientation-dependent etching process on the first semiconductor material to define a plurality of second recesses proximate the gate structure, wherein each of the second recesses has a faceted edge, and forming a first region of stress-inducing semiconductor material in each of the second recesses, wherein each of the first regions of stress-inducing semiconductor material has a faceted edge that engages a corresponding faceted edge in one of the second recesses.Type: ApplicationFiled: January 11, 2012Publication date: July 11, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Chung Foong Tan, Maciej Wiatr, Stephan Kronholz, Falong Zhou, Ying Hao Hsieh
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Publication number: 20110049567Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas.Type: ApplicationFiled: July 22, 2010Publication date: March 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Eric Peng, Chao-Cheng Chen, Ming-Hua Yu, Ying Hao Hsieh, Tze-Liang Lee, Chii-Horng Li, Syun-Ming Jang, Shih-Hao Lo