Patents by Inventor YING HAO SU
YING HAO SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11913925Abstract: A sensing device is provided. The sensing device includes a processing circuit and a multi-sensor integrated single chip. The multi-sensor integrated single chip includes a substrate and a temperature sensor, a pressure sensor, and an environmental sensor disposed on the substrate. The temperature sensor senses temperature. The pressure sensor senses pressure. The environmental sensor senses an environmental state. The processing circuit obtains a first sensed temperature value from the temperature sensor when the environmental sensor does not operate, and it obtains a second sensed temperature value from the temperature sensor when the environmental sensor operates. The processing circuit obtains a sensed pressure value from the pressure sensor. The processing circuit obtains at least one temperature calibration reference of the pressure sensor according to the first and second sensed temperature values and calibrates the sensed pressure value according to the temperature calibration reference.Type: GrantFiled: December 17, 2020Date of Patent: February 27, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ying-Che Lo, Yu-Sheng Lin, Po-Jen Su, Ting-Hao Hsiao
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Publication number: 20220079639Abstract: One embodiment of the disclosure relates to a flexible bone fixation device including two first fixation parts and a first flexible spanning part, connected between the two first fixation parts. The first flexible spanning part has a plurality of first cuts spaced apart by one another.Type: ApplicationFiled: December 4, 2020Publication date: March 17, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Fang-Jie JANG, Pei-I TSAI, An-Li CHEN, Wei-Lun FAN, Shih-Ping LIN, Yi-Hung WEN, De-Yau LIN, Shun-Mao YANG, Ying-Hao SU, Huan-Jang KO
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Patent number: 10515953Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.Type: GrantFiled: October 13, 2017Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
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Publication number: 20180040617Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.Type: ApplicationFiled: October 13, 2017Publication date: February 8, 2018Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9793268Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.Type: GrantFiled: January 24, 2014Date of Patent: October 17, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9697325Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.Type: GrantFiled: June 6, 2016Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su
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Patent number: 9543161Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a flowable-material (FM) layer over a substrate. The substrate has a first region and a second region. A top surface of the FM layer in the first region is higher than a top surface of the FM layer in the second region. The method also includes forming a plurality of trenches in the FM layer in the first region and performing annealing process to reflow the FM layer, wherein the plurality of trenches are filled with the FM layer.Type: GrantFiled: February 10, 2016Date of Patent: January 10, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Hao Su, Yu-Lun Liu, Chi-Kang Chang, Shih-Chi Fu, Kuei-Shun Chen, Chloe Hsu
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Publication number: 20160283644Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Inventors: Shih-Ming CHANG, Ming-Yo CHUNG, Tzu-Chun LO, Ying-Hao SU
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Patent number: 9361420Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.Type: GrantFiled: July 13, 2015Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su
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Publication number: 20150317424Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.Type: ApplicationFiled: July 13, 2015Publication date: November 5, 2015Inventors: Shih-Ming Chang, Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su
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Publication number: 20150214226Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Hao SU, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9081289Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.Type: GrantFiled: March 15, 2013Date of Patent: July 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Ying-Hao Su, Tzu-Chun Lo, Ming-Yo Chung
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Publication number: 20140121799Abstract: A method is provided for validating measurement data, such as data obtained from a scanning electron microscope using in a semiconductor fabrication facility. The method includes applying a signal on a material feature by using a source in a measurement tool having a tool setting parameter, collecting a response signal from the material feature by using a detector in the measurement tool to obtain the measurement data, calculating a simulated response signal by a smart, and validating the measurement data by comparing the collected response signal with the simulated response signal. The system also includes a design database having a design feature, a measurement tool collecting a response signal, and a smart review engine configured to connect the measurement tool and the design database.Type: ApplicationFiled: November 1, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lun Liu, Ying-Hao Su, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 8703392Abstract: The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.Type: GrantFiled: September 4, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lun Liu, Chia-Chu Liu, Kuei-Shun Chen, Chung-Ming Wang, Ying-Hao Su
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Publication number: 20140065554Abstract: The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.Type: ApplicationFiled: September 4, 2012Publication date: March 6, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lun Liu, Chia-Chu Liu, Kuei-Shun Chen, Chung-Ming Wang, Ying-Hao Su
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Patent number: 8508841Abstract: A light conversion module includes a coupler for combining two light beams to form a combined light beam, a nonlinear crystal arranged to receive the combined light beam and configured to include a plurality of poling regions for performing successive nonlinear frequency mixing processes, a first optical device configured to focus the combined light beam onto the nonlinear crystal, a first moving stage carrying the nonlinear crystal and moving the nonlinear crystal for an adjustment of a focus position of the combined light beam on the nonlinear crystal, and an optical detector configured for measuring a power level of the light beam from the nonlinear crystal for the adjustment of the focus position of the combined light beam on the nonlinear crystal.Type: GrantFiled: March 4, 2011Date of Patent: August 13, 2013Assignee: HC Photonic Corp.Inventors: Ming Hsien Chou, Ying Hao Su
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Publication number: 20120224252Abstract: A light conversion module includes a coupler for combining two light beams to form a combined light beam, a nonlinear crystal arranged to receive the combined light beam and configured to include a plurality of poling regions for performing successive nonlinear frequency mixing processes, a first optical device configured to focus the combined light beam onto the nonlinear crystal, a first moving stage carrying the nonlinear crystal and moving the nonlinear crystal for an adjustment of a focus position of the combined light beam on the nonlinear crystal, and an optical detector configured for measuring a power level of the light beam from the nonlinear crystal for the adjustment of the focus position of the combined light beam on the nonlinear crystal.Type: ApplicationFiled: March 4, 2011Publication date: September 6, 2012Applicant: HC PHOTONICS CORP.Inventors: MING HSIEN CHOU, YING HAO SU