Patents by Inventor Ying-Hao Wu
Ying-Hao Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125423Abstract: A projection device includes a housing and a bracket assembly. The housing has a first side wall and a second side wall connected to each other, the first side wall has a connecting portion and a limit groove, the limit groove has a curved section and a linear section connected to each other. The second side wall has a projection hole. The bracket assembly includes an adapter and a bracket. The adapter is movably connected to the connecting portion. The bracket is pivotally connected to the adapter and has a limit post extending into the limit groove. When the limit post moves to the linear section, the adapter is adapted to move in the connecting portion and drives the limit post to move in the linear section, so the bracket can be closer to the projection hole and the effect of covering the projection hole by the bracket is improved.Type: ApplicationFiled: October 13, 2023Publication date: April 18, 2024Inventors: YING ZHANG, CHIH-HAO WU, GANG LI
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Patent number: 11961892Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11929417Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 30, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20240069067Abstract: A test device includes a power compensation module and a test module. The power compensation module receives AC power generated by a device under test to generate DC power to the device under test. The test module provides a plurality of test signals and a test mode to the device under test for testing the device under test.Type: ApplicationFiled: December 5, 2022Publication date: February 29, 2024Inventors: Wei-Chih HUNG, Ying-Ping CHIANG, Yu-Ren RUAN, Chia-Hao WU
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Patent number: 11626292Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.Type: GrantFiled: March 8, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chang Lee, Jiann-Horng Lin, Chih-Hao Chen, Ying-Hao Wu, Wen-Yen Chen, Shih-Hua Tseng, Shu-Huei Suen
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Patent number: 11183392Abstract: According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.Type: GrantFiled: April 28, 2020Date of Patent: November 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jiann-Horng Lin, Chao-Kuei Yeh, Ying-Hao Wu, Tai-Yen Peng, Chih-Hao Chen, Chih-Sheng Tian
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Publication number: 20210193480Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.Type: ApplicationFiled: March 8, 2021Publication date: June 24, 2021Inventors: Yi-Chang LEE, Jiann-Horng LIN, Chih-Hao CHEN, Ying-Hao WU, Wen-Yen CHEN, Shih-Hua TSENG, Shu-Huei SUEN
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Patent number: 10943791Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.Type: GrantFiled: May 31, 2019Date of Patent: March 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chang Lee, Jiann-Horng Lin, Chih-Hao Chen, Ying-Hao Wu, Wen-Yen Chen, Shih-Hua Tseng, Shu-Huei Suen
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Publication number: 20200258754Abstract: According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: JIANN-HORNG LIN, CHAO-KUEI YEH, YING-HAO WU, TAI-YEN PENG, CHIH-HAO CHEN, CHIH-SHENG TIAN
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Publication number: 20200135487Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.Type: ApplicationFiled: May 31, 2019Publication date: April 30, 2020Inventors: Yi-Chang LEE, Jiann-Horng LIN, Chih-Hao CHEN, Ying-Hao WU, Wen-Yen CHEN, Shih-Hua TSENG, Shu-Huei SUEN
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Patent number: 10636667Abstract: A method of manufacturing a semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer on the line-end cut pattern; reducing a width of the line-end cut pattern; etching first horizontal portions of the spacer layer with the reduced line-end cut pattern as an etching mask; removing the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the etched line-end cut pattern as an etch mask.Type: GrantFiled: September 4, 2018Date of Patent: April 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jiann-Horng Lin, Chao-Kuei Yeh, Ying-Hao Wu, Tai-Yen Peng, Chih-Hao Chen, Chih-Sheng Tian
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Patent number: 10340141Abstract: An embodiment method includes defining a first mandrel and a second mandrel over a hard mask layer. The method also includes depositing a spacer layer over and along sidewalls of the first mandrel and the second mandrel, and forming a sacrificial material over the spacer layer between the first mandrel and the second mandrel. The sacrificial material includes an inorganic oxide. The method further includes removing first horizontal portions of the spacer layer to expose the first mandrel and the second mandrel. Remaining portions of the spacer layer provide spacers on sidewalls of the first mandrel and the second mandrel. The method further includes removing the first mandrel and the second mandrel and patterning the hard mask layer using the spacers and the sacrificial material as an etch mask.Type: GrantFiled: July 3, 2017Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Yen Peng, Chao-Kuei Yeh, Ying-Hao Wu, Chih-Hao Chen
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Publication number: 20190157094Abstract: A method of manufacturing a semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer on the line-end cut pattern; reducing a width of the line-end cut pattern; etching first horizontal portions of the spacer layer with the reduced line-end cut pattern as an etching mask; removing the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the etched line-end cut pattern as an etch mask.Type: ApplicationFiled: September 4, 2018Publication date: May 23, 2019Inventors: JIANN-HORNG LIN, CHAO-KUEI YEH, YING-HAO WU, TAI-YEN PENG, CHIH-HAO CHEN, CHIH-SHENG TIAN
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Publication number: 20190131131Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Inventors: Ying-Hao WU, Chao-Kuei YEH, Tai-Yen PENG, Yun-Yu CHEN, Jiann-Horng LIN, Chih-Hao CHEN
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Patent number: 10276378Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.Type: GrantFiled: October 30, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Hao Wu, Chao-Kuei Yeh, Tai-Yen Peng, Yun-Yu Chen, Jiann-Horng Lin, Chih-Hao Chen
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Publication number: 20180315601Abstract: An embodiment method includes defining a first mandrel and a second mandrel over a hard mask layer. The method also includes depositing a spacer layer over and along sidewalls of the first mandrel and the second mandrel, and forming a sacrificial material over the spacer layer between the first mandrel and the second mandrel. The sacrificial material includes an inorganic oxide. The method further includes removing first horizontal portions of the spacer layer to expose the first mandrel and the second mandrel. Remaining portions of the spacer layer provide spacers on sidewalls of the first mandrel and the second mandrel. The method further includes removing the first mandrel and the second mandrel and patterning the hard mask layer using the spacers and the sacrificial material as an etch mask.Type: ApplicationFiled: July 3, 2017Publication date: November 1, 2018Inventors: Tai-Yen Peng, Chao-Kuei Yeh, Ying-Hao Wu, Chih-Hao Chen
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Publication number: 20160102112Abstract: Dinitrosyl iron complexes are disclosed, which are represented by the following formula (I): [(R1R2N(CH2)nNR3(CH2)mNR4R5)Fe(NO)2]z??(I) wherein the definitions of R1, R2, R3, R4, R5, n, m and z are the same as those defined in the specification. In addition, the present invention further provides a use of the aforementioned dinitrosyl iron complexes, and a water splitting device using the same.Type: ApplicationFiled: August 6, 2015Publication date: April 14, 2016Inventors: Wen-Feng LIAW, Tzung-Wen CHIOU, Ying-Hao WU
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Patent number: 5492512Abstract: A brake system for an automobile comprises a planetary gear set, a clutch operating unit and an emergency braking unit. The planetary gear set is disposed between gear and clutch assemblies of the automobile and includes a bell-shaped casing with a central neck connected securely to an input shaft of the gear assembly. The bell-shaped casing has an annular wall portion with an internal thread therein, a sun gear disposed centrally in the casing and fixed to a clutch shaft of the clutch assembly which passes axially and centrally therethrough, and a planet gear which meshes with the internal thread of the casing and the sun gear. The planet gear has a planet shaft connected rotatably to a clutch shell of the clutch assembly.Type: GrantFiled: October 24, 1994Date of Patent: February 20, 1996Assignee: Chung-Da WuInventor: Ying-Hao Wu
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Patent number: 4726600Abstract: A dual system bicycle for hand and foot propelling operations including a handle device with a front link mechanism operatively installed on top of a front fork member fixed on a front wheel of a bicycle, and a lever device with a rear link mechanism movably connected between the front link and a pedal system installed in a lower portion of a frame structure and in the rear wheel through a chain wheel arrangement of the bicycle; thereby, the rider can use both hands and feet for propelling the bicycle, improving his bodily fitness and increasing the moving speed of the bicycle. Alternatively, the dual system bicycle can be easily changed into an ordinary bicycle mode for foot propulsion only.Type: GrantFiled: July 29, 1986Date of Patent: February 23, 1988Inventor: Ying-Hao Wu