Patents by Inventor Ying Hsin Lu
Ying Hsin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11961891Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.Type: GrantFiled: March 21, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
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Patent number: 11949000Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.Type: GrantFiled: July 27, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20230387230Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
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Publication number: 20230207650Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Ru-Shang Hsiao, Ying Hsin Lu, Ching-Hwanq Su, Pin Chia Su, Ling-Sung Wang
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Publication number: 20230145694Abstract: Analog and logic devices may coexist on a common integrated circuit chip, accommodating features with different pitches, linewidths, and pattern densities. Such differences in design and layout at various layers during manufacturing can cause process loading by contributing different amounts of reactants to surface chemical reactions. Such variation in the balance of chemical reactants can result in disparities in film thicknesses within the chip that can affect device performance. Embodiments of the present disclosure disclose a masking sequence that can alleviate process loading disparities during an undercut etch process adjacent to polysilicon structures.Type: ApplicationFiled: June 10, 2022Publication date: May 11, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ling Wu, Ru-Shang Hsiao, I-Shan Huang, Ying Hsin Lu, C.J. Wu
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Patent number: 11588038Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.Type: GrantFiled: February 12, 2021Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ying Hsin Lu, Ching-Hwanq Su, Pin Chia Su, Ling-Sung Wang
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Publication number: 20220367688Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang
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Publication number: 20220367671Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
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Patent number: 11502185Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.Type: GrantFiled: May 22, 2020Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, Ling-Sung Wang
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Publication number: 20220359728Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, Ling-Sung Wang
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Patent number: 11476351Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.Type: GrantFiled: July 30, 2020Date of Patent: October 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang
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Patent number: 11450758Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.Type: GrantFiled: June 12, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
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Publication number: 20220223590Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.Type: ApplicationFiled: November 23, 2021Publication date: July 14, 2022Inventors: Hsi-Jung WU, Sheng-Fu YU, Ru-Shang Hsiao, Ying-Hsin Lu
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Publication number: 20220216317Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.Type: ApplicationFiled: March 21, 2022Publication date: July 7, 2022Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
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Patent number: 11282934Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.Type: GrantFiled: November 22, 2019Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
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Publication number: 20210391441Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
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Publication number: 20210305386Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.Type: ApplicationFiled: February 12, 2021Publication date: September 30, 2021Inventors: Ru-Shang Hsiao, Ying Hsin Lu, Ching-Hwanq Su, Pin Chia Su, Ling-Sung Wang
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Publication number: 20210257481Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.Type: ApplicationFiled: July 30, 2020Publication date: August 19, 2021Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang