Abstract: A display panel including a pixel array and a gate driver circuit is provided. The pixel array has a plurality of pixels. The gate driver circuit is used for providing a plurality of gate signals to the pixels and includes a plurality of shift registers and a plurality of demultiplexers. The shift registers respectively receive a first gate signal of the gate signals and a first clock signal of a plurality of clock signals to respectively provide a first control signal and a second control signal. The demultiplexers respectively receive a plurality of second clock signals of the clock signals, respectively turn-on according to the first control signal provided by the corresponding one of the shift registers, and respectively cut-off according to the second control signal provided by the corresponding one of the shift registers.

Abstract: A display panel including a pixel array and a gate driver circuit is provided. The pixel array has a plurality of pixels. The gate driver circuit is used for providing a plurality of gate signals to the pixels and includes a plurality of shift registers and a plurality of demultiplexers. The shift registers respectively receive a first gate signal of the gate signals and a first clock signal of a plurality of clock signals to respectively provide a first control signal and a second control signal. The demultiplexers respectively receive a plurality of second clock signals of the clock signals, respectively turn-on according to the first control signal provided by the corresponding one of the shift registers, and respectively cut-off according to the second control signal provided by the corresponding one of the shift registers.

Abstract: A thin film transistor including a gate, a channel, a stopper layer, a source and a drain is provided. The channel and the gate are overlapped. The stopper layer covers a portion of the channel and has a ring-shape hole exposing two opposite connecting portions of the channel. A portion of the stopper layer is disposed between the source and the channel and between the drain and the channel. The source and the drain are filled in the ring-shape hole of the stopper layer and electrically connected to the connecting portions of the channel. Moreover, a pixel structure including the thin film transistor is provided.

Abstract: A thin film transistor including a gate, a channel, a stopper layer, a source and a drain is provided. The channel and the gate are overlapped. The stopper layer covers a portion of the channel and has a ring-shape hole exposing two opposite connecting portions of the channel. A portion of the stopper layer is disposed between the source and the channel and between the drain and the channel. The source and the drain are filled in the ring-shape hole of the stopper layer and electrically connected to the connecting portions of the channel. Moreover, a pixel structure including the thin film transistor is provided.

Abstract: A thin film transistor disposed above a carrying surface of a substrate is provided. The thin film transistor includes a gate, a first insulation layer, a channel, a source, a second insulation layer and a drain. The gate and the channel are overlapped with each other in a normal direction of the carrying surface. The first insulation layer is disposed between the channel and the gate. The source covers a portion of the channel and is electrically connected to the portion of the channel. The channel is located between the source and the first insulation layer in the normal direction. The source is disposed between the second insulation layer and the channel. The second insulation layer has a first hole exposing another portion of the channel. The drain is filled in the first hole and electrically connected to the another portion of the channel. Moreover, a pixel structure is provided.

Abstract: The disclosure relates to a pixel circuit which includes an LED, a storage capacitor, a driving transistor, and first to third switching transistors. The driving transistor is utilized to control connection/disconnection between a power supply voltage and the LED. The first switching transistor receives a first scanning signal for controlling connection/disconnection between a gate of the driving transistor and the power supply voltage. The second switching transistor receives a second scanning signal for controlling connection/disconnection between the storage capacity and a ground voltage. The third switching transistor receives the first scanning signal for controlling connection/disconnection between the storage capacity and a data voltage. The first scanning signal and the second scanning signal are in antiphase to each other. A driving method thereof is also disclosed.

Abstract: A capacitive touch display panel includes a first substrate, a second substrate, an opaque pattern, a plurality of transparent conductive sensor pads, and a plurality of non-transparent conductive patterns. The first substrate and the second substrate are disposed oppositely. The transparent conductive sensor pads are disposed on the second substrate. The non-transparent conductive patterns are disposed on the second substrate, and the non-transparent conductive patterns and the transparent conductive sensor pads are electrically connected and overlapping. The conductivity of the non-transparent conductive patterns is higher than that of the transparent conductive sensor pads, and the non-transparent conductive patterns are corresponding to the opaque pattern.

Abstract: A white balance calibration method includes providing red light, green light, blue light, and white light to a display panel according to first image data; detecting a first temperature of a backlight module when the backlight module provides the red light, green light, blue light, and white light to the display panel; detecting whether luminance of white light of each pixel is lower than maximum luminance of a white light emitting diode (LED) corresponding to the pixel when a first difference between the first temperature and a standard temperature stored in a lookup table is less than a predetermined value; controlling the backlight module to turn on a red LED, a green LED, and a blue LED corresponding to the pixel during turning-on of the white light if the luminance of the white light is lower than the maximum luminance of the white LED corresponding to the pixel.

Abstract: A liquid crystal display device includes a plurality of gate lines, a plurality of data lines, a pixel array, a gate driver, a timing controller, and an optimization circuit. Each pixel unit in the pixel array displays images according to the gate driving signal received from a corresponding gate line and the data driving signal received from a corresponding data line. According to an optimized reference value, the timing controller provides an output enable signal, based on which the gate driver outputs the gate driving signals. The optimization circuit receives a first grayscale data related to display images of a row of pixel units in a first driving period and a second grayscale data related to display images of the row of pixel units in a second driving period, and provides the optimized reference value according the difference between the first and second grayscale data.

Abstract: A transistor array substrate includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units. The scan lines and the data lines are all disposed on the substrate. Each pixel unit includes a transistor and a pixel electrode. The transistor is electrically connected to the pixel electrodes, the scan lines and the data lines. Each transistor includes a gate, a drain, a source, a metal-oxide-semiconductor layer and a channel protective layer. A channel gap exists between the drain and the source. The metal-oxide-semiconductor layer has a pair of side edges opposite to each other and the side edges are located at two ends of the channel gap. The channel protective layer covers the metal-oxide-semiconductor layer in the channel gap and protrudes from the side edges of the metal-oxide-semiconductor layer.

Abstract: A manufacturing method of a thin film transistor is provided. An insulating pattern layer having at least one protrusion is formed on a substrate. At least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. The spacer and the amorphous semiconductor patterns are crystallized. The protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. A carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.

Abstract: A manufacturing method of a thin film transistor is provided. An insulating pattern layer having at least one protrusion is formed on a substrate. At least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. The spacer and the amorphous semiconductor patterns are crystallized. The protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. A carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.

Abstract: A thin film transistor and a manufacturing method thereof are provided. An insulating pattern layer having at least one protrusion is formed on a substrate. Afterwards, at least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. Later, the spacer and the amorphous semiconductor patterns are crystallized. Subsequently, the protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. Then, a carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.

Abstract: A display apparatus and a display panel. The display panel includes a first scanning line, a plurality of second scanning lines, a plurality of first pixels and a plurality of second pixels. The first scanning line receives a first scanning signal. The second scanning lines receive a second scanning signal, where the second scanning signal is different from the first scanning signal. The first pixels are coupled to the corresponding second and first scanning lines. The second pixels are coupled to the two corresponding second scanning lines respectively. By adjusting a capacitance of a capacitor, a voltage level of the second scanning signal, or a line impedance of the second scanning line, a pixel voltage difference of the first pixel equals to a pixel voltage difference of the second pixel.

Abstract: A method for driving a liquid crystal display device is disclosed. The liquid crystal display device includes a plurality of scan lines, a plurality of data lines, and a plurality of pixel units. Each one of the pixel units is corresponding to one of the scan lines and one of the data lines. The method includes: turning on at least two of the scan lines at the same time, said at least two scan lines being separated from each other by at least one turned off scan line, and said at least two scan lines respectively coupled to distinct one or multiple of the data lines; and transmitting respective image data to the data lines which are coupled to said at least two scan lines. The present invention can solve problems of bad performance and errors in a display image.

Abstract: A liquid crystal display device includes a plurality of gate lines, a plurality of data lines, a pixel array, a gate driver, a timing controller, and an optimization circuit. Each pixel unit in the pixel array displays images according to the gate driving signal received from a corresponding gate line and the data driving signal received from a corresponding data line. According to an optimized reference value, the timing controller provides an output enable signal, based on which the gate driver outputs the gate driving signals. The optimization circuit receives a first grayscale data related to display images of a row of pixel units in a first driving period and a second grayscale data related to display images of the row of pixel units in a second driving period, and provides the optimized reference value according the difference between the first and second grayscale data.

Abstract: A capacitive touch display panel includes a first substrate, a second substrate, an opaque pattern, a plurality of transparent conductive sensor pads, and a plurality of non-transparent conductive patterns. The first substrate and the second substrate are disposed oppositely. The transparent conductive sensor pads are disposed on the second substrate. The non-transparent conductive patterns are disposed on the second substrate, and the non-transparent conductive patterns and the transparent conductive sensor pads are electrically connected and overlapping. The conductivity of the non-transparent conductive patterns is higher than that of the transparent conductive sensor pads, and the non-transparent conductive patterns are corresponding to the opaque pattern.

Abstract: A thin film transistor and a manufacturing method thereof are provided. An insulating pattern layer having at least one protrusion is formed on a substrate. Afterwards, at least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. Later, the spacer and the amorphous semiconductor patterns are crystallized. Subsequently, the protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. Then, a carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.

Abstract: An LCD panel includes a plurality of signal lines, a plurality of display units, a driving circuit and a test unit. Each display unit is coupled to a corresponding signal line of the plurality of signal lines. The driving circuit is coupled to corresponding signals lines via a plurality of output ends. The test unit includes a shorting bar, a test pad, and a plurality of switches. Each switch is coupled between a corresponding signal line of the plurality of signal lines and the shorting bar.

Abstract: A method of adjusting the brightness of a display device is provided. The method includes providing a plurality of saturated level-adjust voltages to various level adjustments of the display device when the central brightness is saturated. Then, a computation of the saturated level-adjust voltage of each level adjustment is carried out to obtain a display voltage of each level adjustment. Thereafter, a computation of the saturated level-adjust voltage, a common voltage and the display voltage of each level adjustment is carried out to obtain a feed-through voltage for each level adjustment. After that, a computation of the feed-through voltage and the saturated level-adjust voltage of each level adjustment is carried out to obtain a liquid crystal capacitance value for each level adjustment. Finally, a simulation of the liquid crystal capacitance value of each level adjustment is carried out to obtain an optimized level-adjust voltage for each level adjustment.