Patents by Inventor Ying-Jen Lin

Ying-Jen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150097093
    Abstract: The present invention provides a supporter assembly and a related display device. The display panel includes a first connecting portion. The supporter includes a first body and a second body. The first body includes a first inclined surface and a second connecting portion pivotably connected to the first connecting portion. The second body includes a second inclined surface adjacent to the first inclined surface. An end of the pivot portion is connected to the first inclined surface, and the other end is connected to the second inclined surface. The first inclined surface and the second inclined surface pivot to each other via the pivot portion, and the first body is able to pivot relative to the second body. Comparing to the prior art, the present invention can switch the operation modes of the supporter assembly and the related display device according to user's demand for the preferred touch operation.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Top Victory Investments Ltd.
    Inventors: Yu-Hung Tsai, Ying Jen LIN, I-Ting CHIANG
  • Publication number: 20020182824
    Abstract: A method of forming shallow trench isolation (STI) uses a flowable insulating layer. In the method, a pad oxide layer is first formed on a substrate. A stop layer is formed on the pad oxide layer. Then, a trench is formed in the stop layer, the pad oxide layer and the substrate. A liner oxide layer is formed on the inner surface of the trench. Thereafter, a flowable insulating layer, such as a doped silicon oxide layer, is formed in the trench. An insulating layer, such as a silicon oxide layer, is formed on the flowable insulating layer. Finally, the stop layer and the pad oxide layer are removed so as to completely form shallow trench isolation.
    Type: Application
    Filed: June 5, 2001
    Publication date: December 5, 2002
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Jen Lin, Joe Ko, Gary Hong, Yen-Lin Ding
  • Patent number: 5976935
    Abstract: A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: November 2, 1999
    Assignee: United Semiconductor Corp.
    Inventors: Ying-Jen Lin, Joe Ko, Gary Hong