Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.

Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.

Abstract: Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.

Abstract: A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

Abstract: First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.

Abstract: A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.

Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

Abstract: A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.

Abstract: A method includes forming a first package component, which includes an interposer, and a first die bonded to a first side of the interposer. A second die is bonded to a second side of the interposer. The second die includes a substrate, and a through-via penetrating through the substrate. The method further includes bonding a second package component to the first package component through a first plurality of solder regions. The first package component is further electrically connected to the second package component through the through-via in the second die. The second die is further bonded to the second package component through a second plurality of solder regions.

Abstract: Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.

Abstract: A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.