Patents by Inventor Ying-Ju Chen

Ying-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220007547
    Abstract: A kit for forming a data center comprising a first rack, a second rack, a first support having a first end and a second end opposite the first end, the first support configured to be secured to the floor at the first end, a cooling frame having a cooling unit received therein, the cooling frame having a first face and a second face opposite the first face, the cooling frame configured to be secured to the second end of the first support, a first distribution frame having a first plurality of support arms extending therefrom, the first distribution frame configured to be coupled to the first face of the cooling frame, and a second distribution frame having a second plurality of support arms extending therefrom, the second distribution frame configured to be coupled to the second face of the cooling frame.
    Type: Application
    Filed: July 2, 2020
    Publication date: January 6, 2022
    Inventors: Soheil Farshchian, Angela Ying-Ju Chen, Winnie Leung, Pascal C. Kam, Kenneth Dale Shaul
  • Patent number: 11211289
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20210391413
    Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20210391168
    Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Tzuan-Horng Liu, Ying-Ju Chen
  • Publication number: 20210388046
    Abstract: A chimeric signal peptide for protein expression includes an N-region, a hydrophobic region, and a C-region, wherein the N-region and the C-region are from a same signal peptide of a first protein and the hydrophobic region is from a signal peptide of a second protein, wherein the first protein is different from the second protein. The first and second protein are independently selected from the group consisting of BM40, IL2, HA, Insulin, CD33, IFNA2, IgGK leader, AZU, and SEAP.
    Type: Application
    Filed: December 23, 2019
    Publication date: December 16, 2021
    Applicant: Development Center for Biotechnology
    Inventors: Chao-Yi TENG, Ying-Ju CHEN
  • Patent number: 11195804
    Abstract: A semiconductor structure includes a first interconnect structure, a second interconnect structure, a molding, a first seal ring and a second seal ring. The molding surrounds the die. The molding and the die are disposed between the first interconnect structure and the second inter connect structure. The first seal ring is disposed in the first interconnect structure. The second seal ring is disposed in the second interconnect structure.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: December 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20210366773
    Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 11183475
    Abstract: A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Patent number: 11177201
    Abstract: In an embodiment, a package includes a first package structure including a first integrated circuit die having an active side and a back-side, the active side including die connectors, a second integrated circuit die adjacent the first integrated circuit die, the second integrated circuit die having an active side and a back-side, the active side including die connectors, a routing die including die connectors bonded to the active sides of the first integrated circuit die and the second integrated circuit die, the routing die electrically coupling the first integrated circuit die to the second integrated circuit die, an encapsulant encapsulating the first integrated circuit die, the second integrated circuit die, and the routing die, and a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the second integrated circuit die.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Publication number: 20210351130
    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.
    Type: Application
    Filed: July 2, 2021
    Publication date: November 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jie CHEN, Ying-Ju CHEN, Hsien-Wei CHEN, Der-Chyang YEH, Chen-Hua YU
  • Patent number: 11164857
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Publication number: 20210335735
    Abstract: One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Publication number: 20210335722
    Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.
    Type: Application
    Filed: August 28, 2020
    Publication date: October 28, 2021
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Ming-Fa Chen
  • Publication number: 20210313254
    Abstract: Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
  • Publication number: 20210305209
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, a second semiconductor die, an insulating layer, and a first dual-damascene connector electrically connected to the first semiconductor die. The first semiconductor die includes a first bonding surface including a die attaching region and a peripheral region connected to the die attaching region. The second semiconductor die is electrically connected to the first semiconductor die, and a second bonding surface of the second semiconductor die is bonded to the first bonding surface in the die attaching region. The insulating layer disposed on the first bonding surface in the peripheral region extends along sidewalls of the second semiconductor die. The first dual-damascene connector includes a first portion disposed on the insulating layer, and a second portion penetrating through the insulating layer and landing on the first bonding surface in the peripheral region.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11133304
    Abstract: A device includes a first die and a second die. The first die includes: a first substrate that contains first electrical circuitry, a first interconnection structure disposed over the first substrate, a first dielectric layer disposed over the first interconnection structure, and a plurality of first bonding pads disposed over the first dielectric layer. The second die includes: a second substrate that contains second electrical circuitry, a second interconnection structure disposed over the second substrate, a second dielectric layer disposed over the second interconnection structure, and a plurality of second bonding pads disposed over the second dielectric layer. The first bonding pads of the first die are bonded to the second bonding pads of the second die. At least one of the first die or the second die includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes more than two metal layers that are stacked over one another.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 11107680
    Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Tzuan-Horng Liu, Ying-Ju Chen
  • Patent number: 11081391
    Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 11056433
    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Der-Chyang Yeh, Chen-Hua Yu
  • Publication number: 20210159224
    Abstract: A device includes a first die and a second die. The first die includes: a first substrate that contains first electrical circuitry, a first interconnection structure disposed over the first substrate, a first dielectric layer disposed over the first interconnection structure, and a plurality of first bonding pads disposed over the first dielectric layer. The second die includes: a second substrate that contains second electrical circuitry, a second interconnection structure disposed over the second substrate, a second dielectric layer disposed over the second interconnection structure, and a plurality of second bonding pads disposed over the second dielectric layer. The first bonding pads of the first die are bonded to the second bonding pads of the second die. At least one of the first die or the second die includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes more than two metal layers that are stacked over one another.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Inventors: Hsiang-Ku Shen, Ying-Ju Chen, Hsien-Wei Chen