Abstract: A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.

Abstract: In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled "T". The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function.

Abstract: An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.

Abstract: An electrically erasable floating gate storage cell (EPROM) is disclosed which comprises a body of single crystal silicon semiconductor material having a substrate of one conductivity type, a source region and a drain region each of a second conductivity type, a channel region of the first conductivity type connecting the source region and drain region, a polycrystalline silicon layer conductively connected to either the source region or the drain region, a conductive insulated floating gate which partially overlies and is separated from the polycrystalline silicon layer by a layer of silicon dioxide and a control gate which overlies and is separated from the floating gate by a layer of silicon dioxide. Fowler-Nordheim tunneling current occurs between the polycrystalline layer and the floating gate during programming and erasing of the EPROM. The floating gate influences the conductivity of the channel region in accordance with the charge stored thereon during programming.