Patents by Inventor Ying-Kai CHOU

Ying-Kai CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10276679
    Abstract: A semiconductor device including a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer is provided. The substrate has a first conductive type. The first doped region is formed in the substrate and has a second conductive type. The second doped region is formed in the substrate and has the second conductive type. The gate is formed on the substrate and is disposed between the first and second doped regions. The gate dielectric layer is formed on the substrate and is disposed between the gate and the substrate. The gate dielectric layer includes a first region and a second region. The depth of the first region is different from the depth of the second region.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 30, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Wei Chiu, Hsing-Chao Liu, Chun-Fu Liu, Ying-Kai Chou
  • Patent number: 10276563
    Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a patterned mask on a substrate, wherein the patterned mask includes a pad oxide layer and a silicon nitride layer over the pad oxide layer. The method also includes forming a trench in the substrate by performing a first etching process on the substrate through an opening of the patterned mask and forming a dielectric material layer in the trench, in the opening, and on the patterned mask. The method further includes performing a planarization process to remove the dielectric material layer outside of the trench, and performing a heat treatment process to form an oxidized portion at the interface of the pad oxide layer and the substrate and adjacent to the dielectric material layer.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: April 30, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ying-Kai Chou, Li-Che Chen, Hsing-Chao Liu
  • Publication number: 20180350931
    Abstract: A semiconductor device including a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer is provided. The substrate has a first conductive type. The first doped region is formed in the substrate and has a second conductive type. The second doped region is formed in the substrate and has the second conductive type. The gate is formed on the substrate and is disposed between the first and second doped regions. The gate dielectric layer is formed on the substrate and is disposed between the gate and the substrate. The gate dielectric layer includes a first region and a second region. The depth of the first region is different from the depth of the second region.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chien-Wei CHIU, Hsing-Chao LIU, Chun-Fu LIU, Ying-Kai CHOU
  • Publication number: 20180076282
    Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a patterned mask on a substrate, wherein the patterned mask includes a pad oxide layer and a silicon nitride layer over the pad oxide layer. The method also includes forming a trench in the substrate by performing a first etching process on the substrate through an opening of the patterned mask and forming a dielectric material layer in the trench, in the opening, and on the patterned mask. The method further includes performing a planarization process to remove the dielectric material layer outside of the trench, and performing a heat treatment process to form an oxidized portion at the interface of the pad oxide layer and the substrate and adjacent to the dielectric material layer.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 15, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Ying-Kai CHOU, Li-Che CHEN, Hsing-Chao LIU