Patents by Inventor Ying Lai

Ying Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12376364
    Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wei Hsu, Pei Ying Lai, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Patent number: 12336273
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure over a first region of a substrate and forming a second fin structure over a second region of a substrate, forming a first gate dielectric layer around the first fin structure and forming a second gate dielectric layer around the second fin structure, forming a barrier layer over the first gate dielectric layer, treating the substrate with a first fluorine-containing gas, forming a work function layer over the second gate dielectric layer after treating the substrate with the first fluorine-containing gas, and treating the substrate with a second fluorine-containing gas after forming the work function layer over the second gate dielectric layer.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Tsung-Da Lin, Chi On Chui
  • Publication number: 20250186409
    Abstract: The invention relates to a 5-aminohexahydro-6,7,8-trihydroxy-3H-oxazo-lo[3,4-a]pyridin-3-one (i.e. 2,3,4-trihydroxy-5N,6O-oxomethylidene-nojirimycin-1-amine) glycol-ipid mimetic derivative of formula (I) acting as antagonists or agonist of the TLR4 for the treatment and/or prevention of an immune disease such as e.g. acute inflammation, chronic disease allergy, the Metabolic Syndrome, non-alcoholic fatty liver disease (NAFLD), non-alcoholic steatohepatitis (NASH), immune mediated hepatitis, an autoimmune disease, graft rejection pathology, inflammatory bowel disease, atherosclerosis and airway hyperactivity, such as e.g. asthma and allergic rhinitis. An exemplary compound is e.g. example 1, compound (1).
    Type: Application
    Filed: October 26, 2022
    Publication date: June 12, 2025
    Inventors: José Manuel GARCÍA FERNÁNDEZ, Carmen ORTIZ MELLET, Manuel GONZÁLEZ CUESTA, Elena Matilde SÁNCHEZ FERNÁNDEZ, Ya-Jen CHANG, Alan Chuan-Ying LAI
  • Publication number: 20250163122
    Abstract: Polypeptide constructs comprising a first peptide attached to a cell penetrating peptide, wherein the first peptide has both homology to a portion of the SNARE protein SNAP-25 and non-natural amino acids comprising one or two macrocyclic crosslinks, are provided herein. These polypeptide constructs are useful for disrupting the primary interface between SNAP-25 or its homolog and Syt1 or its homolog. Methods for treating a subject with mucus hypersecretion-based airway obstruction and/or developed mucus occlusions are also described, as well as methods of inhibiting mucin secretion in an airway epithelial cell.
    Type: Application
    Filed: February 16, 2023
    Publication date: May 22, 2025
    Inventors: Burton F. DICKEY, Michael J. TUVIM, Philip JONES, Axel T. BRUNGER, Ying LAI, Manfred FRICK
  • Publication number: 20250154165
    Abstract: The invention relates to a multiantennary glycolipid mimetics of formula (I), wherein X, Y, Z and R1 are defined in the description, or a pharmaceutical composition thereof and their use as a medicament, particularly, for the treatment and/or prevention of an immune disease cursed by Th1/Th2 imbalance. Further the invention relates to a vaccine which comprises a compound of formula (I).
    Type: Application
    Filed: October 24, 2022
    Publication date: May 15, 2025
    Inventors: José Manuel GARCÍA FERNÁNDEZ, Carmen ORTIZ MELLET, Manuel GONZÁLEZ CUESTA, Irene HERRERA GONZÁLEZ, Ya-Jen CHANG, Alan Chuan-Ying LAI
  • Publication number: 20250133759
    Abstract: A method forming a source/drain region based on a first portion of a semiconductor region, forming a high-k dielectric layer based on a second portion of the semiconductor region, forming a dipole film on the high-k dielectric layer, performing a treatment process on the dipole film using a process gas comprising nitrogen and hydrogen, performing a drive-in process to drive a dipole dopant in the dipole film into the high-k dielectric layer, and depositing a work-function layer on the high-k dielectric layer.
    Type: Application
    Filed: January 23, 2024
    Publication date: April 24, 2025
    Inventors: Chun-Hsiu Chiang, Pei Ying Lai, Cheng-Hao Hou, Chi On Chui, Shan-Mei Liao, Hung-Chi Wu
  • Patent number: 12272629
    Abstract: Devices and methods of manufacture for a hybrid interposer within a semiconductor device. A semiconductor device may include a package substrate and a hybrid interposer. The hybrid interposer may include an organic interposer material layer, and a non-organic interposer material layer positioned between the organic interposer material layer and the package substrate. The semiconductor device may further include an integrated device positioned within the hybrid interposer. In one embodiment, the integrated device may be positioned within the organic interposer material layer. In another embodiment, the integrated device may be positioned within the non-organic interposer material layer. In a further embodiment, the integrated device may be positioned within the organic interposer material layer and the non-organic interposer material layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Monsen Liu, Shuo-Mao Chen, Po-Ying Lai, Shang-Lun Tsai, Shin-Puu Jeng
  • Patent number: 12231844
    Abstract: A microphone system of the invention is applicable to an electronic device comprising an adjustable mechanism that causes a change in geometry of a microphone array. The microphone system comprises the microphone array, a sensor and a beamformer. The microphone array comprises multiple microphones that detect sound and generate multiple audio signals. The sensor detects a mechanism variation of the electronic device to generate a sensing output. The beamformer is configured to perform a set of operations comprising: performing a spatial filtering operation over the multiple audio signals using a trained model based on the sensing output, one or more first sound sources in one or more desired directions and one or more second sound sources in one or more undesired directions to generate a beamformed output signal originated from the one or more first sound sources.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: February 18, 2025
    Assignee: BRITISH CAYMAN ISLANDS INTELLIGO TECHNOLOGY INC.
    Inventors: Hua-Jun Hong, Chih-Sheng Chen, Hsueh-Ying Lai, Yu-Pao Tsai, Tsung-Liang Chen
  • Patent number: 12219329
    Abstract: A microphone system for a boomless headset is disclosed, comprising a microphone array and a processing unit. The microphone array comprises Q microphones and generates Q audio signals. A first microphone and a second microphone are disposed on different earcups, and a third microphone is disposed on one of two earcups and displaced laterally and vertically from one of the first and the second microphones. The processing unit performs operations comprising: performing spatial filtering over the Q audio signals using a trained model based on an arc line with a vertical distance and a horizontal distance from a midpoint between the first and the second microphones, a time delay range for the first and the second microphones and coordinates of the Q microphones to generate a beamformed output signal originated from zero or more target sound sources inside a target beam area, where Q>=3.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: February 4, 2025
    Assignee: BRITISH CAYMAN ISLANDS INTELLIGO TECHNOLOGY INC.
    Inventors: Hsueh-Ying Lai, Chih-Sheng Chen, Hua-Jun Hong, Chien Hua Hsu, Tsung-Liang Chen
  • Publication number: 20240427389
    Abstract: Examples herein relate to ambient noise level detection. For instance, in some examples an electronic device includes a cooling resource and a processor resource to alter an operational speed of the cooling resource from an initial operational speed to a first altered operational speed, detect an ambient noise level, compare the ambient noise level to a first noise threshold, and restrict the operational speed of the cooling resource to be less than the initial operational speed.
    Type: Application
    Filed: September 15, 2021
    Publication date: December 26, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: CHIH-WEI HUANG, YI-YING LAI, CHIH-LING WEI, HUNG HUA PENG, DAVIS MATTHEW CASTILLO, CHING YU
  • Publication number: 20240413692
    Abstract: A motor includes a rotor and a stator. The stator includes a stator core, and at least one coil module that is wound on the stator core. Each of the at least one coil module includes a plurality of first winding sets that are wound on the stator core. Each of the first winding sets includes a first end and a second end. For each of the at least one coil module, the first ends respectively of the first winding sets are electrically connected to each other, and the second ends respectively of the first winding sets are electrically connected to each other, such that the first winding sets are connected in parallel.
    Type: Application
    Filed: April 8, 2024
    Publication date: December 12, 2024
    Inventors: MAO-YING LAI, JIA-HAO LAI
  • Patent number: 12147163
    Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: November 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Hsieh, Kuan-Ying LAi, Chang-Mao Wang, Chien-Hao Chen, Chun-Chi Yu
  • Publication number: 20240379449
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first n-type transistor having a first threshold voltage and including a first gate dielectric layer, and a second n-type transistor having a second threshold voltage and including a second gate dielectric layer. The first threshold voltage is lower than the second threshold. Each of the first gate dielectric layer and the second gate dielectric layer contains fluorine and hafnium. The first gate dielectric layer has a first average fluorine concentration and a first average hafnium concentration. The second gate dielectric layer has a second average fluorine concentration and a second average hafnium concentration. A first ratio of the first average fluorine concentration to the first average hafnium concentration is greater than and a second ratio of the second average fluorine concentration to the second average hafnium concentration.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei Ying LAI, Chia-Wei HSU, Tsung-Da LIN, Chi On CHUI
  • Publication number: 20240379842
    Abstract: The present disclosure provides a semiconductor device, including a substrate, a first dopant region in the substrate, wherein the first dopant is doped with a first conductivity type dopant, a first drift region at a top surface of the substrate, a first drain region adjacent to the first drift region, a second drain region, wherein an upper portion of the first dopant region is between the first drain region and the second drain region, and a first conductive layer connecting the first drain region, the second drain region, and a top surface of the upper portion of the first dopant region, wherein a Schottky barrier interface is formed between the top surface of the upper portion of the first dopant region and the first conductive layer.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Inventors: YU-YING LAI, PO-CHIH SU, RUEY-HSIN LIU
  • Publication number: 20240379516
    Abstract: Methods of manufacture for a hybrid interposer within a semiconductor device. A method of forming a semiconductor structure may include forming a package substrate and forming a hybrid interposer. Forming a hybrid interposer may include depositing a non-organic interposed material layer over the package substrate and depositing an organic interposer material layer over the non-organic interposer material layer.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Monsen LIU, Shuo-Mao CHEN, Po-Ying LAI, Shang-Lun TSAI, Shin-Puu JENG
  • Patent number: 12143782
    Abstract: A microphone system is disclosed, comprising: a microphone array and a processing unit. The microphone array comprises Q microphones that detect sound and generate Q audio signals. The processing unit is configured to perform operations comprising: spatial filtering over the Q audio signals using a trained model based on at least one target beam area (TBA) and coordinates of the Q microphones to generate a beamformed output signal originated from ? target sound source inside the at least one TBA, where ?>=0. Each TBA is defined by r time delay ranges for r combinations of two microphones out of the Q microphones, where Q>=3 and r>=1. A dimension of a first number for locations of all sound sources able to be distinguished by the processing unit increases as a dimension of a second number for a geometry formed by the Q microphones increases.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: November 12, 2024
    Assignee: BRITISH CAYMAN ISLANDS INTELLIGO TECHNOLOGY INC.
    Inventors: Hsueh-Ying Lai, Chih-Sheng Chen, Chien-Hua Hsu, Hua-Jun Hong, Tsung-Liang Chen
  • Publication number: 20240347606
    Abstract: Dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. The dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. The nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Pei Ying LAI, Cheng-Chieh LIN, Hsueh-Ju CHEN, Tsung-Da LIN, Cheng-Hao HOU, Chi On CHUI
  • Publication number: 20240339446
    Abstract: Damage to an LDMOS transistor from voltage overshoot in a power switching circuit operating at high switching speeds is prevented by embedding a diode under a drain region of the LDMOS transistor. The embedded diode is doped more heavily than a drift region of the LDMOS transistor and lowers a breakdown voltage of the LDMOS transistor.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Inventors: Yu-Ying Lai, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20240332004
    Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing an aluminum nitride layer on the gate dielectric, depositing an aluminum oxide layer on the aluminum nitride layer, performing an annealing process to drive aluminum in the aluminum nitride layer into the gate dielectric, removing the aluminum oxide layer and the aluminum nitride layer, and forming a gate electrode on the gate dielectric.
    Type: Application
    Filed: July 3, 2023
    Publication date: October 3, 2024
    Inventors: Chi On Chui, Cheng-Hao Hou, Da-Yuan Lee, Pei Ying Lai, Yi Hsuan Chen, Jia-Yun Xu
  • Publication number: 20240322040
    Abstract: A first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. A second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.
    Type: Application
    Filed: September 29, 2023
    Publication date: September 26, 2024
    Inventors: Pei Ying Lai, Yi Hsuan Chen, Yen-Fu Chen, Jia-Yun Xu, Cheng-Hao Hou, Da-Yuan Lee, Chi On Chui