Abstract: A display panel control method, a display mode of the display panel including a normal display mode and a partial highlight display mode, the control method including obtaining display information of a display area in the display panel in the partial highlight display mode, the display information including a grayscale displayed corresponding to each pixel, and a number of pixels displaying the corresponding grayscale; determining a target gamma curve based on the display information, a difference between a display brightness corresponding to the grayscale in the target gamma curve and a target display brightness required for the pixels to display the corresponding grayscale in the partial highlight display mode being within a predetermined range; and controlling the pixels in the display area to display based on the target gamma curve.

Abstract: Examples herein relate to ambient noise level detection. For instance, in some examples an electronic device includes a cooling resource and a processor resource to alter an operational speed of the cooling resource from an initial operational speed to a first altered operational speed, detect an ambient noise level, compare the ambient noise level to a first noise threshold, and restrict the operational speed of the cooling resource to be less than the initial operational speed.

Abstract: A method of using a coupling system includes aligning an optical fiber with a cavity in a chip, wherein aligning the optical fiber comprises orienting the fiber within an angle ranging from about 88-degrees to about 92-degrees with respect to a top surface of the chip. The method further includes emitting an optical signal from the optical fiber. The method further includes redirecting the optical signal into a waveguide using a grating positioned on an opposite side of the cavity from the optical fiber.

Abstract: A motor includes a rotor and a stator. The stator includes a stator core, and at least one coil module that is wound on the stator core. Each of the at least one coil module includes a plurality of first winding sets that are wound on the stator core. Each of the first winding sets includes a first end and a second end. For each of the at least one coil module, the first ends respectively of the first winding sets are electrically connected to each other, and the second ends respectively of the first winding sets are electrically connected to each other, such that the first winding sets are connected in parallel.

Abstract: A method of making a photonic device includes depositing a cladding layer over a silicon layer. The method further includes patterning the cladding layer to expose a first portion of the silicon layer, wherein a second portion of the silicon layer is covered by the patterned cladding layer, and a waveguide portion is in the second portion of the silicon layer. The method further includes depositing a low refractive index layer directly over the patterned cladding layer, wherein a refractive index of the low refractive index layer is less than a refractive index of silicon nitride.

Abstract: An electronic device including a foldable touch display panel and a driver circuit is provided. The foldable touch display panel includes a foldable substrate and a plurality of touch sensors. The foldable substrate includes a first portion and a second portion. The first portion and the second portion face each other in a folded state. The driver circuit is coupled to the foldable touch display panel. The driver circuit is configured to drive the foldable touch display panel to perform a touch sensing operation in a touch sensing state. The driver circuit is configured to determine a folding angle between the first portion and the second portion according to a capacitance variation of the touch sensors in the folded state.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; two adjacent radiation-sensing regions formed in the substrate; and a trench isolation structure extending from the back surface of the substrate into the substrate between the two adjacent radiation-sensing regions. The trench isolation structure includes: a dielectric material; a first film being formed between the dielectric material and the substrate; a second film being formed between the first film and the dielectric material; and a third film being formed between the second film and the dielectric material. An electronegativity of the first film, an electronegativity of the second film and an electronegativity of the third film are different from each other.

Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

Abstract: Methods of manufacture for a hybrid interposer within a semiconductor device. A method of forming a semiconductor structure may include forming a package substrate and forming a hybrid interposer. Forming a hybrid interposer may include depositing a non-organic interposed material layer over the package substrate and depositing an organic interposer material layer over the non-organic interposer material layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first n-type transistor having a first threshold voltage and including a first gate dielectric layer, and a second n-type transistor having a second threshold voltage and including a second gate dielectric layer. The first threshold voltage is lower than the second threshold. Each of the first gate dielectric layer and the second gate dielectric layer contains fluorine and hafnium. The first gate dielectric layer has a first average fluorine concentration and a first average hafnium concentration. The second gate dielectric layer has a second average fluorine concentration and a second average hafnium concentration. A first ratio of the first average fluorine concentration to the first average hafnium concentration is greater than and a second ratio of the second average fluorine concentration to the second average hafnium concentration.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a first dopant region in the substrate, wherein the first dopant is doped with a first conductivity type dopant, a first drift region at a top surface of the substrate, a first drain region adjacent to the first drift region, a second drain region, wherein an upper portion of the first dopant region is between the first drain region and the second drain region, and a first conductive layer connecting the first drain region, the second drain region, and a top surface of the upper portion of the first dopant region, wherein a Schottky barrier interface is formed between the top surface of the upper portion of the first dopant region and the first conductive layer.

Abstract: A microphone system is disclosed, comprising: a microphone array and a processing unit. The microphone array comprises Q microphones that detect sound and generate Q audio signals. The processing unit is configured to perform operations comprising: spatial filtering over the Q audio signals using a trained model based on at least one target beam area (TBA) and coordinates of the Q microphones to generate a beamformed output signal originated from ? target sound source inside the at least one TBA, where ?>=0. Each TBA is defined by r time delay ranges for r combinations of two microphones out of the Q microphones, where Q>=3 and r>=1. A dimension of a first number for locations of all sound sources able to be distinguished by the processing unit increases as a dimension of a second number for a geometry formed by the Q microphones increases.

Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a grating on a first side of a semiconductor layer, wherein the grating is configured to receive the optical signal. The coupling system further includes an interconnect structure over the grating on the first side of the semiconductor layer, wherein the interconnect structure defines a cavity aligned with the grating. The coupling system further includes a first polysilicon layer on a second side of the semiconductor layer, wherein the second side of the semiconductor layer is opposite to the first side of the semiconductor layer.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: Dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. The dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. The nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon.

Abstract: Damage to an LDMOS transistor from voltage overshoot in a power switching circuit operating at high switching speeds is prevented by embedding a diode under a drain region of the LDMOS transistor. The embedded diode is doped more heavily than a drift region of the LDMOS transistor and lowers a breakdown voltage of the LDMOS transistor.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing an aluminum nitride layer on the gate dielectric, depositing an aluminum oxide layer on the aluminum nitride layer, performing an annealing process to drive aluminum in the aluminum nitride layer into the gate dielectric, removing the aluminum oxide layer and the aluminum nitride layer, and forming a gate electrode on the gate dielectric.

Abstract: A display panel and an operation method of the display panel are provided. The display panel includes a display area and a frame area. The display area is configured to display an image. During a touch sensing period, the display area and the frame area emit an uplink signal to perform an active stylus touch detection operation.

Abstract: A first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. A second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.